clk: tegra: Use fence_udelay() during PLLU init

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This patch uses fence_udelay rather than udelay during PLLU
initialization to ensure writes to clock registers happens before
waiting for specified delay.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Sowjanya Komatineni 2019-08-16 12:41:58 -07:00 • committed by Thierry Reding

parent a99d744d8c

commit f68cbb3578

1 changed files with 4 additions and 4 deletions

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drivers/clk/tegra/clk-tegra210.c

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