drm/i915/chv: Don't do group access reads from TX lanes either

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Like PCS, TX group reads return 0xffffffff. So we need to target each
lane separately if we want to use RMW cycles to update the registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2014-04-09 13:29:03 +03:00 • committed by Daniel Vetter

parent 97fd4d5c81

commit f72df8dbe2

3 changed files with 59 additions and 29 deletions

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11

drivers/gpu/drm/i915/i915_reg.h

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49

drivers/gpu/drm/i915/intel_dp.c

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28

drivers/gpu/drm/i915/intel_hdmi.c

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