net: axienet: Autodetect 64-bit DMA capability

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When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.

To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.

The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Andre Przywara 2020-03-24 13:23:46 +00:00 • committed by David S. Miller

parent 4e958f33ee

commit f735c40ed9

2 changed files with 27 additions and 0 deletions

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1

drivers/net/ethernet/xilinx/xilinx_axienet.h

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26

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

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