clk: renesas: r8a7795: Correct lvds clock parent

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According to the latest information, the parent clock of the LVDS module
clock is the S0D4 clock, not the S2D1 clock.

Note that this change has no influence on actual operation, as the
rcar-du LVDS encoder driver doesn't use the parent clock's rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

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Geert Uytterhoeven 2016-06-10 09:36:44 +02:00

parent a209568042

commit f7bb887fb8

1 changed files with 1 additions and 1 deletions

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drivers/clk/renesas/r8a7795-cpg-mssr.c

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