clk: tegra: dfll: round down voltages based on alignment

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When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.

Based on the work of Penny Chiu <pchiu@nvidia.com>.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

...

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Joseph Lo 2019-01-04 11:06:50 +08:00 • committed by Thierry Reding

parent 36541f0499

commit f7ebf8874c

1 changed files with 13 additions and 8 deletions

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drivers/clk/tegra/clk-dfll.c

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