clk: at91: sama7g5: decrease lower limit for MCK0 rate

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On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Claudiu Beznea 2020-11-19 17:43:14 +02:00 • committed by Stephen Boyd

parent 4011f03ee4

commit f803858af8

1 changed files with 1 additions and 1 deletions

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drivers/clk/at91/sama7g5.c

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