From f80c812804c3c07b891594cfc3db02326cba36aa Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Tue, 9 Jun 2026 12:52:37 +0300 Subject: [PATCH] drm/i915/display: harden shifts in ICL_DPCLKA_CFGCR0_DDI_CLK_SEL macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ICL_DPCLKA_CFGCR0 has a 2-bit DDI_CLK_SEL field per combo PHY, for PHY_A..PHY_D only. Any other phy value (PHY_NONE, TypeC/SNPS PHYs) is not valid here. This is not a problem with the current implementation, because phy is always valid when these macros are called, but it's more robust to cast to unsigned so the shift is always well-defined. Reviewed-by: Michał Grzelak Link: https://patch.msgid.link/20260609095525.570614-3-luciano.coelho@intel.com Signed-off-by: Luca Coelho --- .../gpu/drm/i915/display/intel_display_regs.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 0f5018482497..f98f76b308de 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2874,9 +2874,19 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ (tc_port) + 12 : \ (tc_port) - TC_PORT_4 + 21)) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + +/* + * ICL_DPCLKA_CFGCR0 has a 2-bit DDI_CLK_SEL field per combo PHY, for + * PHY_A..PHY_D only. Any other phy value (PHY_NONE, TypeC/SNPS PHYs) + * is not valid here. + */ +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy & 0x3, 0, 2, 4, 6) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + REG_GENMASK(ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) + 1, \ + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))