PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values

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The value that should be programmed into the PADS_REFCLK register varies
per SoC.  Fix the Tegra PCIe driver to program the correct values.  Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The ASIC team has validated all these values, except for the Tegra20 value
which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>

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Stephen Warren 2016-07-25 16:02:27 -05:00 • committed by Bjorn Helgaas

parent cf5d318012

commit f814430c3e

1 changed files with 8 additions and 13 deletions

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drivers/pci/host/pci-tegra.c

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