drm/bridge: tc358767: Limit the Pixel PLL input range

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According to new configuration spreadsheet from Toshiba for TC9595,
the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
calculates those PLL input clock as reference clock divided by both
pre-dividers. Add the extra limit.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240118220243.203655-1-marex@denx.de

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Marek Vasut 2024-01-18 23:02:31 +01:00 • committed by Robert Foss

parent 71fc3249f5

commit f86ae204be

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drivers/gpu/drm/bridge/tc358767.c

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