From f86bed1bc93111a0308bc4d0335ee68d6fc9a1f4 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Thu, 22 Jan 2026 10:18:58 +0530 Subject: [PATCH] drm/i915/cx0: Clear response ready & error bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS before writing the transaction pending bit of PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done we find that the PHY hangs since it ends up in a weird state if left idle for more than 1 hour. Bspec: 65101 Signed-off-by: Suraj Kandpal Reviewed-by: Gustavo Sousa Reviewed-by: Michał Grzelak Link: https://patch.msgid.link/20260122044859.753682-1-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4f56a370102d..ff74f64eb970 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -223,6 +223,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder, return -ETIMEDOUT; } + intel_clear_response_ready_flag(encoder, lane); + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | XELPDP_PORT_M2P_COMMAND_READ | @@ -294,6 +296,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder, return -ETIMEDOUT; } + intel_clear_response_ready_flag(encoder, lane); + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), XELPDP_PORT_M2P_TRANSACTION_PENDING | (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :