mmc: sdhci-pci: Fix S0i3 for Intel BYT-based controllers

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Tuning can leave the IP in an active state (Buffer Read Enable bit set)
which prevents the entry to low power states (i.e. S0i3). Data reset will
clear it.

Generally tuning is followed by a data transfer which will anyway sort out
the state, so it is rare that S0i3 is actually prevented.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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Adrian Hunter 2018-02-14 15:57:43 +02:00 • committed by Ulf Hansson

parent 4a3928c6f8

commit f8870ae6e2

1 changed files with 31 additions and 4 deletions

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drivers/mmc/host/sdhci-pci-core.c

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