perf/x86/intel: Add mem-loads/stores support for Haswell

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mem-loads is basically the same as Sandy Bridge,
but we use a separate string for changes later.

Haswell doesn't support the full precise store mode,
so we emulate it using the "DataLA" facility.
This allows to do everything, but for data sources we
can only detect L1 hit or not.

There is no explicit enable bit anymore, so we have
to tie it to a perf internal only flag.

The address is supported for all memory related PEBS
events with DataLA. Instead of only logging for the
load and store events we allow logging it for all
(it will be simply 0 if the current event does not
support it)

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <ak@linux.jf.intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/1371515812-9646-7-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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This commit is contained in:

Andi Kleen 2013-06-17 17:36:52 -07:00 • committed by Ingo Molnar

parent 135c5612c4

commit f9134f36ae

3 changed files with 41 additions and 7 deletions

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6

arch/x86/kernel/cpu/perf_event.h

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10

arch/x86/kernel/cpu/perf_event_intel.c

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32

arch/x86/kernel/cpu/perf_event_intel_ds.c

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