ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7

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The current implementation of the dcache_line_size macro reads the L1
cache size from the CCSIDR register. This, however, is not guaranteed to
be the smallest cache line in the cache hierarchy. The patch changes to
the macro to use the more architecturally correct CTR register.

Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Catalin Marinas 2010-12-07 16:52:04 +01:00 • committed by Russell King

parent 6313e3c217

commit f91e2c3bd4

1 changed files with 6 additions and 6 deletions

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arch/arm/mm/proc-macros.S

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