clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP

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Add clocks, resets and power domains for ADC IP available on the Renesas
RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20241206111337.726244-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Claudiu Beznea 2024-12-06 13:13:23 +02:00 • committed by Geert Uytterhoeven

parent 548f9a3c3e

commit f962745289

1 changed files with 7 additions and 0 deletions

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drivers/clk/renesas/r9a08g045-cpg.c

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