drm/radeon: implement async vm_flush for the CP (v7)

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Update the page table base address and flush the
VM TLB using the CP.

v2: update for 2 level PTs
v3: use new packet for invalidate
v4: update SH_MEM* regs when flushing the VM
v5: add pfp sync, go back to old style vm TLB invalidate
v6: fix hdp flush packet count
v7: use old style HDP flush

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Alex Deucher 2012-08-31 10:37:47 -04:00

parent fbc832c7f5

commit f96ab48457

1 changed files with 79 additions and 0 deletions

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drivers/gpu/drm/radeon/cik.c

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