drm/amd/display: Change the delay time before enabling FEC

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[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.

[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173 us. So using 7 microseconds delay instead of
1 miliseconds.

Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Leo (Hanghong) Ma 2019-11-07 16:30:04 -05:00 • committed by Alex Deucher

parent 728a506823

commit fa11d3c942

1 changed files with 8 additions and 1 deletions

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drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

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