drm/i915: Skip CS verification of L3 bank registers

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Access to 0xb100 - 0xb3ff mmio range is controlled by the MCR selector
which only affects CPU MMIO. Therefore these registers cannot be realiably
read with MI_SRM from the command streamer so skip their verification.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717180624.20354-5-tvrtko.ursulin@linux.intel.com

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Tvrtko Ursulin 2019-07-17 19:06:22 +01:00

parent 6c2b0103ad

commit fa380486d5

1 changed files with 33 additions and 5 deletions

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38

drivers/gpu/drm/i915/gt/intel_workarounds.c

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