drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2

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On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY
to take effect in VRR mode. Can't really think of a reason why we'd
ever disable that chicken bit, so let's just always set it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230320203352.19515-4-ville.syrjala@linux.intel.com
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

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This commit is contained in:

Ville Syrjälä 2023-03-20 22:33:49 +02:00

parent b25e07419f

commit fa9e4fce52

2 changed files with 9 additions and 2 deletions

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8

drivers/gpu/drm/i915/display/intel_vrr.c

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3

drivers/gpu/drm/i915/i915_reg.h

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