clk: samsung: exynos7: Fix CMU TOPC block clock

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Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Alim Akhtar 2015-08-26 09:00:41 +05:30 • committed by Sylwester Nawrocki

parent 6ff33f3902

commit fa9f3a5264

1 changed files with 6 additions and 6 deletions

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drivers/clk/samsung/clk-exynos7.c

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