usb: dwc3: workaround: U1/U2 -> U0 transiton

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RTL revisions <1.83a have an issue where, depending
on the link partner, the USB link might do multiple
entry/exit of low power states before a transfer
takes place causing degraded throughput.

The suggested workaround is to clear bits
12:9 of DCTL register if we see a transition
from U1|U2 to U0 and only re-enable that on
a transfer complete IRQ and we have no pending
transfers on any of the enabled endpoints.

Signed-off-by: Felipe Balbi <balbi@ti.com>

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This commit is contained in:

Felipe Balbi 2011-10-14 13:00:30 +03:00

parent d39ee7be2a

commit fae2b904aa

2 changed files with 76 additions and 2 deletions

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2

drivers/usb/dwc3/core.h

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76

drivers/usb/dwc3/gadget.c

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