ARM: dts: r8a7790: Add L2 cache-controller nodes

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Add device nodes for the L2 caches, and link the CPU nodes to them.

The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

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Geert Uytterhoeven 2015-06-02 14:31:39 +02:00 • committed by Simon Horman

parent c86a4b6219

commit fb1cecd406

1 changed files with 20 additions and 0 deletions

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arch/arm/boot/dts/r8a7790.dtsi

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