Merge branch 'pci/controller/xilinx-ecam'

Browse source

- Drop xilinx-nwl updates of bridge bus number fields, since PCI core
  already does that (Thippeswamy Havalige)

- Update xilinx-nwl driver and ECAM size in devicetree example to allow up
  to 256 buses (Thippeswamy Havalige)

* pci/controller/xilinx-ecam:
  PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
  PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
  dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
  PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields

...

This commit is contained in:

Bjorn Helgaas 2023-10-28 13:31:02 -05:00

parent a4179c60a9 2fccd11518

commit fb3d102fc2

2 changed files with 4 additions and 16 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml

View file

18

drivers/pci/controller/pcie-xilinx-nwl.c

View file