Blackfin: handle BF561 Core B memory regions better when SMP=n

Rather than assume Core B is always run with caches turned on, let people
load into any of the on-chip memory regions.  It is their business how the
SRAM/Cache regions are utilized, so don't prevent them from being able to
load into them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2009-06-29 14:20:10 -04:00
commit fb4b5d3a37
2 changed files with 29 additions and 8 deletions