drm/amd/display: Add NULL test for 'timing generator' in 'dcn21_set_pipe()'

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In "u32 otg_inst = pipe_ctx->stream_res.tg->inst;"
pipe_ctx->stream_res.tg could be NULL, it is relying on the caller to
ensure the tg is not NULL.

Fixes: 474ac4a875 ("drm/amd/display: Implement some asic specific abm call backs.")
Cc: Yongqiang Sun <yongqiang.sun@amd.com>
Cc: Anthony Koo <Anthony.Koo@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Srinivasan Shanmugam 2024-01-31 08:49:41 +05:30 • committed by Alex Deucher

parent 886571d217

commit fb5a3d0370

1 changed files with 14 additions and 10 deletions

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drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

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