drm/amd/display: Embed DCN2 SOC bounding box

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[Why]
In order to support uclk switching on NV10 the SOC bounding box
needs to be updated.

[How]
We currently read the constants from the gpu info FW, but supporting
workarounds in DC for different versions of the FW adds additional
complexity to the codebase.

NV10 has been released so it's cleanest to keep the bounding box and
source code in sync by embedding the bounding box like we do for
other ASICs.

Fixes: 02316e963a ("drm/amd/display: Force uclk to max for every state")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nicholas Kazlauskas 2019-07-30 09:08:34 -04:00 • committed by Alex Deucher

parent 1a2c29bce0

commit fb6959ae50

1 changed files with 112 additions and 2 deletions

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114

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

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