drm/i915: Disable DDR DVFS on CHV

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DDR DVFS introduces massive memory latencies which can't be handled by
the PND deadline stuff. Instead the watermarks will need to be
programmed to compensate for the latency and the deadlines will need to
be programmed to tight fixed values. That means DDR DVFS can only be
enabled if the display FIFOs are large enough, and that pretty much
means we have to manually repartition them to suit the needs of the
moment.

That's a lot of change, so in the meantime let's just disable DDR DVFS
to get the display(s) to be stable.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2015-03-05 21:19:52 +02:00 • committed by Daniel Vetter

parent cfb41411fc

commit fc1ac8dee1

2 changed files with 39 additions and 0 deletions

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5

drivers/gpu/drm/i915/i915_reg.h

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34

drivers/gpu/drm/i915/intel_pm.c

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