clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2

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pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.

Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

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Mark Zhang 2013-08-07 19:25:08 +08:00 • committed by Peter De Schrijver

parent d17cb95fa0

commit fc20eeff6c

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drivers/clk/tegra/clk-tegra114.c

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