drm/i915/icl: Configure lane sequencing of combo phy transmitter

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This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.

v2: Rebase
v3: Add empty line to make code more legible (Ville).

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-2-git-send-email-madhav.chauhan@intel.com

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Madhav Chauhan 2018-09-16 16:23:24 +05:30 • committed by Jani Nikula

parent 945ac78928

commit fc41001d97

1 changed files with 39 additions and 0 deletions

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drivers/gpu/drm/i915/icl_dsi.c

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