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ASoC: Intel: Skylake: Disable clock and power gating during FW/LIB download

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In order to achieve better DMA performance and reduce download time for
firmware and library, it is recommended to disable dynamic clock and
power gating. In some scenarios, DMA may wait to accumulate more data and
last chunk of data never gets completed if dynamic clock and power
gating is kept enabled.

This patch adds support to disable/enable dynamic clock and power gating
and use it during firmware and library download.

Signed-off-by: Rakesh Ughreja <rakesh.a.ughreja@intel.com>
Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com>
Signed-off-by: Guneshwor Singh <guneshwor.o.singh@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sanyog Kale 2018-03-13 09:02:25 +05:30 • committed by Mark Brown
commit fc9fdd61c4
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5 changed files with 46 additions and 2 deletions
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