ARM: 6772/1: errata: possible fault MMU translations following an ASID switch

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On the r2p* and r3p* versions of the Cortex-A9, a speculative memory
access may cause a page table walk which starts prior to an ASID switch
but completes afterwards. This can populate the micro-TLB with a stale
entry which may be hit with the new ASID.

This workaround places two dsb instructions in the mm switching code so
that no page table walks can cross the ASID switch.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Will Deacon 2011-02-28 18:15:16 +01:00 • committed by Russell King

parent f5412be599

commit fcbdc5fe6e

2 changed files with 17 additions and 0 deletions

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arch/arm/Kconfig

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6

arch/arm/mm/proc-v7.S

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