PCI: support sizing P2P bridge I/O windows with 1K granularity

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Some bridges support I/O windows with 1K alignment, not just the 4K
alignment defined by the PCI spec.  For example, see the IOBL_ADR register
and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2).

This patch adds support for sizing the window in 1K increments based
on the requirements of downstream devices.

[bhelgaas: changelog, comment]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

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This commit is contained in:

Yinghai Lu 2012-07-09 19:55:29 -06:00 • committed by Bjorn Helgaas

parent 2b28ae1912

commit fd59134110

1 changed files with 22 additions and 6 deletions

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28

drivers/pci/setup-bus.c

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