drm/i915/execlists: Trust the CSB

Browse source

Now that we use the CSB stored in the CPU friendly HWSP, we do not need
to track interrupts for when the mmio CSB registers are valid and can
just check where we read up to last from the cached HWSP. This means we
can forgo the atomic bit tracking from interrupt, and in the next patch
it means we can check the CSB at any time.

v2: Change the splitting inside reset_prepare, we only want to lose
testing the interrupt in this patch, the next patch requires the change
in locking

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-8-chris@chris-wilson.co.uk

...

This commit is contained in:

Chris Wilson 2018-06-28 21:12:10 +01:00

parent 3800cd1953

commit fd8526e509

4 changed files with 9 additions and 40 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

11

drivers/gpu/drm/i915/i915_irq.c

View file

8

drivers/gpu/drm/i915/intel_engine_cs.c

View file

29

drivers/gpu/drm/i915/intel_lrc.c

View file

1

drivers/gpu/drm/i915/intel_ringbuffer.h

View file