clk: renesas: r9a07g044: Fix P1 Clock

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As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions for P1.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-06-26 09:13:37 +01:00 • committed by Geert Uytterhoeven

parent e93c137361

commit fd8c3f6c36

1 changed files with 3 additions and 3 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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