perf/x86: Add Intel Tiger Lake uncore support

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For MSR type of uncore units, there is no difference between Ice Lake
and Tiger Lake. Share the same code with Ice Lake.

Tiger Lake has two MCs. Both of them are located at 0:0:0. The BAR
offset is still 0x48. The offset of the two MCs is 0x10000.
Each MC has three counters to count every read/write/total issued by the
Memory Controller to DRAM. The counters can be accessed by MMIO.
They are free-running counters.

The offset of counters are different for TIGERLAKE_L and TIGERLAKE.
Add separated mmio_init() functions.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20200206161527.3529-1-kan.liang@linux.intel.com

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Kan Liang 2020-02-06 08:15:27 -08:00 • committed by Ingo Molnar

parent db278b90c3

commit fdb6482244

3 changed files with 173 additions and 0 deletions

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12

arch/x86/events/intel/uncore.c

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2

arch/x86/events/intel/uncore.h

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159

arch/x86/events/intel/uncore_snb.c

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