clk: tegra: pll: Add code to handle if resets are supported by PLL

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If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Bill Huang 2015-06-18 17:28:26 -04:00 • committed by Thierry Reding

parent 407254da29

commit fde207eb15

2 changed files with 16 additions and 0 deletions

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12

drivers/clk/tegra/clk-pll.c

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4

drivers/clk/tegra/clk.h

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