pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28

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Add the missing port pins P19 to P28 for RZ/Five SoC. These additional
pins provide expanded capabilities and are exclusive to the RZ/Five SoC.

Couple of port pins have different configuration and are not identical for
the complete port so introduce struct rzg2l_variable_pin_cfg to handle
such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config
is then assigned in rzg2l_pinctrl_get_variable_pin_cfg().

Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins
which support interrupt facility.

While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK().

Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must
match the driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Lad Prabhakar 2024-01-29 13:55:55 +00:00 • committed by Geert Uytterhoeven

parent 15e4ae4f9a

commit fea58424e2

2 changed files with 208 additions and 9 deletions

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4

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

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213

drivers/pinctrl/renesas/pinctrl-rzg2l.c

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