defxx: Correct DEFEA's ESIC MMIO decoding

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Use ESIC's memory area 1 (MEMCS1) and its Memory Address High Compare
and Memory Address Low Compare registers to set up the MMIO range for
decoding accesses to PDQ ASIC registers.  Previously the PDQ ASIC was
thought to be addressable with the memory area 0 (MEMCS0) and its Memory
Address Compare and Memory Address Mask registers.

The MMIO range allocated for the option card is preset via ECU (EISA
Configuration Utility) and can be disabled, so handle such a case
gracefully too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Maciej W. Rozycki 2014-11-21 14:09:57 +00:00 • committed by David S. Miller

parent a65da0c3da

commit fef85fc466

2 changed files with 39 additions and 24 deletions

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61

drivers/net/fddi/defxx.c

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2

drivers/net/fddi/defxx.h

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