clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate

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The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These
clocks are usually the only downstream clock from Video PLL on i.MX8MP.
Allow these clocks to reconfigure the Video PLL, as that results in
accurate pixel clock. If the Video PLL is not reconfigured, the pixel
clock accuracy is low.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

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Marek Vasut 2024-05-31 22:26:26 +02:00 • committed by Abel Vesa

parent 2c3499c761

commit ff06ea04e4

2 changed files with 6 additions and 2 deletions

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4

drivers/clk/imx/clk-imx8mp.c

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4

drivers/clk/imx/clk.h

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