iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices

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The AMD IOMMU specification Rev 3.00 (December 2016) introduces a
new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register
offset 0030h (IOMMU Extended Feature Register).

When EPHSup=1, the IOMMU hardware requires the PPR bit of the
device table entry (DTE) to be set in order to support PPR for a
particular endpoint device.

Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for
this revision of the AMD IOMMU specification.

Signed-off-by: Gary R Hook <gary.hook@amd.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>

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Gary R Hook 2017-12-20 09:47:08 -07:00 • committed by Alex Williamson

parent f9fc049ef1

commit ff18c4e598

2 changed files with 17 additions and 5 deletions

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20

drivers/iommu/amd_iommu.c

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2

drivers/iommu/amd_iommu_types.h

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