clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568

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The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or
cpll. gpll and cpll also drive many other clocks, so changing the
dclk_vop[012] clocks could change these other clocks as well. Drop
CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can
only adjust the pixel clocks with the divider between the PLL and the
dclk_vop[012] which means the user may have to adjust the PLL clock to a
suitable rate using the assigned-clock-rate device tree property.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220126145549.617165-25-s.hauer@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Sascha Hauer 2022-01-26 15:55:46 +01:00 • committed by Heiko Stuebner

parent 842f4cb726

commit ff3187eabb

1 changed files with 3 additions and 3 deletions

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drivers/clk/rockchip/clk-rk3568.c

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