net/mlx5: Add RS FEC histogram infrastructure

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Define the Ports Phy Histogram Configuration Register (PPHCR) to expose
RS-FEC histogram bin ranges, and expose a new counter group in the Ports
Performance Counters Register (PPCNT) to report the corresponding
histogram values.

Co-developed-by: Yael Chemla <ychemla@nvidia.com>
Signed-off-by: Yael Chemla <ychemla@nvidia.com>
Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1756884600-520195-1-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

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Carolina Jubran 2025-09-03 10:30:00 +03:00 • committed by Leon Romanovsky

parent 04a3134f88

commit ff97bc38be

3 changed files with 31 additions and 0 deletions

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1

include/linux/mlx5/device.h

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1

include/linux/mlx5/driver.h

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29

include/linux/mlx5/mlx5_ifc.h

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