arm64: dts: qcom: x1e80100: Describe the SDHC controllers

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The X Elite platform features two SDHC v5 controllers.

Describe the controllers along with the pin configuration in TLMM
for the SDC2, since they are hardwired and cannot be muxed to any
other function. The SDC4 pin configuration can be muxed to different
functions, so leave those to board specific dts.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org
[bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Abel Vesa 2024-12-12 18:50:39 +02:00 • committed by Bjorn Andersson

parent 89fc83a947

commit ffb21c1e19

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arch/arm64/boot/dts/qcom/x1e80100.dtsi

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