This adds DT nodes for the Cortex-A9 MPCore SCU, local watchdog and
most importantly the global timer.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Cortex-A9 PMU has no associated memory ranges and "make dtbs W=1" warns
about missing reg or ranges property. To avoid the warning, move the PMU
node out of soc subtree to the root.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Use the correct trigger type for Cortex-A9. This was fixed for several
other SoCs since the kernel started issuing a boot-time warning.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
>From the hardware perspective, the actual pclk of the AO uarts
is the corresponding clkc_ao uart gate, not the main clock controller clk81.
This was not problem so far, because the uart_gate had
the CLK_IGNORE_UNUSED flag, which kept the gate open.
We plan to remove the CLK_IGNORE_UNUSED flag in another patch,
but before doing that, we need to fix the clock in the DTS file.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This add the AO (Always-On part) clock DT info for Meson-AXG SoC
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[khilman: cleanup subject]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson into v4.18/dt64
First round of binding update for meson clocks targeted at v4.18
# gpg: Signature made Wed May 16 01:23:15 2018 PDT
# gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Can't check signature: No public key
* tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson:
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
dt-bindings: clock: meson8b: export the NAND clock
Currently there are no differences between the MACH_MESON8 and
MACH_MESON8B Kconfig symbols (except the help text). Since both
platforms are very similar (Meson8b being a slightly updated,
cost-reduced version of Meson8 which even shares some peripherals with
Meson8m2) no notable differences are expected in the future either.
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Currently there are two identical Kconfig options where only differences
are the Kconfig help text and the list of .dtbs that are built:
- MACH_MESON8
- MACH_MESON8B
Build the Meson8b .dtbs when MACH_MESON8 is selected to get rid of the
latter Kconfig symbol later.
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The i2c AO is used for the MIC daughter card of the S400 board
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the pins related to the i2c AO controller of the meson-axg platform
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The clock specified for the i2c AO controller is the one for the EE
domain, which is incorrect as this controller needs the clock for AO
i2c controller.
Fixes: dc6f858e26 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Remove undocumented and unused "clk_i2c" clock name and the second
interrupt from i2c nodes of meson-axg platform. Those seems to have
been copy/pasted from the vendor kernel
Fixes: dc6f858e26 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the UFS QMP phy node and the UFS host controller node, now that we
have working UFS and the necessary clocks in place.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This is pure-churn and should be a no-op. I'm doing it in the hopes
of reducing merge conflicts. When things are sorted in a sane way
(and by base address seems sane) then it's less likely that future
patches will cause merge conflicts.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Let's keep the reserved-memory node tidy and neat and keep it sorted
by address. This should have no functional change.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add command DB node based on the bindings example.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The RPMh clock driver assumes that the xo_board clock is named
"xo_board", not "xo-board". Add a "clock-output-names" property to
the device tree to get the right name.
Also add the proper speed for the xo-clock as 38400000. This is
internally divided in RPMh clock driver to get "bi_tcxo" at 19200000.
After this change the clock tree in /sys/kernel/debug/clk/clk_summary
looks much better.
NOTES:
- Technically you could argue that this clock could belong in board
.dts files, not in the SoC one. However at the moment it's believed
that 100% of sdm845 boards will have an external clock at 38.4. It
can always be moved later if necessary.
- We could rename the "xo-board" device tree node to "xo_board" to
achieve the same effect as this patch. Presumably device-tree folks
would rather keep node names using dashes though.
- We could change the RPMh clock driver to use a dash to achieve the
same effect as this patch, but all other clocks in the clock tree
use underscores. It seems silly to change just this one.
Fixes: 7bafa643647f ("arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add all the necessary dt nodes to support SMEM driver
on SDM845. It also adds the required memory carveouts
so that the kernel does not access memory that is in
use.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch add the node to support APSS shared
mailbox on SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Thierry Escande <thierry.escande@linaro.org>
Tested-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicetree@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds missing microSD card supplies, without this uSD
card will not be detected.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add binding document for serial bluetooth chips using Qualcomm protocol.
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a new serial node for the Qualcomm BT controller QCA6174. This
allows automatic probing and hci registration through the serdev
framework instead of relying on the userspace helpers.
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch enables regulators and gpios for the Qualcomm QCA6174 BT/WLAN
combo controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The node name for a PCIe host bridge must be "pcie" as required by
the binging. dtc now warns about it:
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb: Warning (pci_bridge): /soc/agnoc@0/qcom,pcie@610000: node name is not "pci" or "pcie"
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
arch/arm64/boot/dts/qcom/msm8996-mtp.dtb: Warning (pci_bridge): /soc/agnoc@0/qcom,pcie@610000: node name is not "pci" or "pcie"
arch/arm64/boot/dts/qcom/msm8996-mtp.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
This renames the nodes as appropriate.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
With the addition of this ramoops node it enables post mortem
analysis if a debug cable is not attached and/or not available.
All addresses and values were extracted from CAF AOSP marshmallow
DR 1.6.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This enables SDHCI on the Nexus 5X as well creates common smd_rpm node
which can be shared between both 5X and 6P as per HW design.
Given the lack of documentation, only downstream code was used as a reference
and it eludes to the fact that 8994-rpm-regulator is common between both msm8992
& msm8994. [ see msm.git branch: msm-angler-3.10-marshmallow-mr1, msm8992.dtsi]
At this early stage of development it makes sense for the 8994-rpm-regulator
to be common until data / documentation suggests otherwise.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
Currently used card is KLMAG2GEND, wired to MMC2 slot.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The touchscreen driver no longer configures the device as wakeup source by
default. A "wakeup-source" property is needed.
To avoid regressions, this patch changes the DTS files for the only two
users of this driver that didn't have this property yet.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On RDU1, sdhc1 is used for eMMC, and that is 3.3V only.
Thus configure device node not to probe it as SD/SDIO and not try 1.8V.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Vybrid has single internal temperature sensor connected to both internal
ADC modules.
vf610-zii-dev already has ADC0 enabled. Now, to get temperature sensor
captured by iio_hwmon driver, need to configure iio_hwmon node to use
that ADC.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch uses "operating-points-v2" instead of
"operating-points" to be more fit with cpufreq-dt
driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i.MX7S does NOT support CPU frequency scaling, so no
need to specify the CPU regulator supply.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Correct CPU supply name to meet cpufreq-dt driver's
requirement for voltage scaling.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
On RDU1, imx51 usbh1 interface is either not used, or used via external
block that breaks USB2 signalling.
To keep things working if high-speed device gets connected to that
block, use ChipIdea feature to limit port to full speed.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove unit-address and reg property from anatop regulators to fix
the following DTC warnings with W=1:
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140)
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)
arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There are some LED's attached to the GPIO expander, and
there are is a bank of switches attached to the GPIO expander.
This patch associates the LED and the switches to it.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is a tca6416 GPIO expander on i2c2. This patch enables the
GPIO expander which has several LED's and some connected DIP
switches
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pin control information for the NAND interface on the Armada
98DX3236 and variants.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Use the new bindings of the Marvell NAND controller driver. Also adapt
the NAND controller node organization to distinguish which property is
relevant for the controller, and which one is NAND chip specific. Expose
the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore
as the new driver activates the arbiter by default for all boards which
is either needed or harmless.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Use the new bindings of the Marvell NAND controller driver. Also adapt
the NAND controller node organization to distinguish which property is
relevant for the controller, and which one is NAND chip specific. Expose
the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, not needed anymore
as the new driver activates the arbiter by default for all boards which
is either needed or harmless.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
