On exynos mcpm systems the firmware is hardcoded to jump to an address
in SRAM (0x02073000) when secondary CPUs come up. By default the
firmware puts a bunch of code at that location. That code expects the
kernel to fill in a few slots with addresses that it uses to jump back
to the kernel's entry point for secondary CPUs.
Originally (on prerelease hardware) this firmware code contained a
bunch of workarounds to deal with boot ROM bugs. However on all
shipped hardware we simply use this code to redirect to a kernel
function for bringing up the CPUs.
Let's stop relying on the code provided by the bootloader and just
plumb in our own (simple) code jump to the kernel. This has the nice
benefit of fixing problems due to the fact that older bootloaders
(like the one shipped on the Samsung Chromebook 2) might have put
slightly different code into this location.
Once suspend/resume is implemented for systems using exynos-mcpm we'll
need to make sure we reinstall our fixed up code after resume. ...but
that's not anything new since IRAM (and thus the address of the
mcpm_entry_point) is lost across suspend/resume anyway.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
we need to release dapm widget list after dpcm_path_get in
soc_dpcm_runtime_update. otherwise, there will be potential memory
leak. add dpcm_path_put to fix it.
Signed-off-by: Qiao Zhou <zhouqiao@marvell.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
We use regmap regulator ops to enable/disable and check if regulator
is enabled for various SMPS. However, these depend on valid
enable_reg, enable_mask and enable_value in regulator descriptor.
Currently we do not populate these for SMPS other than SMPS10, this
results in spurious results as regmap assumes that the values are
valid and ends up reading register 0x0 RTC:SECONDS_REG on Palmas
variants that do have RTC! To fix this, we update proper parameters
for the descriptor fields.
Further, we want to ensure the behavior consistent with logic
prior to commit dbabd624d4, where, once you do a set_mode,
enable/disable ensure the logic remains consistent and configures
Palmas to the configuration that we set with set_mode (since the
configuration register is common). To do this, we can rely on the
regulator core's regulator_register behavior where the regulator
descriptor pointer provided by the regulator driver is stored. (no
reallocation and copy is done). This lets us update the enable_value
post registration, to remain consistent with the mode we configure as
part of set_mode.
Fixes: dbabd624d4 ("regulator: palmas: Reemove open coded functions with helper functions")
Reported-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
- Move buffer pointer and length setup to the top,
- Make unsigned values unsigned,
- Loop over words and increment pointers instead of recalculating them,
which allows to kill bytes_done.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@linaro.org>
- Add a timeout when waiting for the transfer complete interrupt,
- If sh_msiof_spi_stop() fails, there's no need to clear IER, as the
interrupt handler has already done that,
- Propagate transfer failures in sh_msiof_transfer_one().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@linaro.org>
Based on an old patch by Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@linaro.org>
Let memory subsystem handle the error logging.
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Let memory subsystem do the error logging.
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Reviewed-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch moves the devm_spi_register_master below the initialization of the
runtime_pm. If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Passing unsigned int pointers as u32 ponters may be dangerous on 64-bit
system.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Do not fail if the exact BLCK rate can not be produced, just print a
warning. Check that sysclk frequency is set before implicitly setting
the BCLK divider.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fixes build with SND_DAVINCI_SOC or SND_OMAP_SOC alone and adds build
dependecy to SND_DAVINCI_SOC or SND_OMAP_SOC.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
of_get_child_by_name expects of_node_put be called when done.
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
last two bits of ADC and limit values are zero and should not be reported
(ad7993, ad7997); compare with read_raw()
event values are 10 (ad7993, ad7997) or 12 bit max., check the range on write
Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net>
Cc: Stable@vger.kernel.org
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
The following commit:
89d7e5c mmc: sdhci-esdhc-imx: add runtime pm support
has the effect of also disabling the hardware card detect
in runtime pm.
We switch to GPIO based detection to avoid this issue.
This patch is based on:
ARM: dts: imx51-babbage: Fix esdhc setup
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Since commit 89d7e5c131 (mmc: sdhci-esdhc-imx: add runtime pm
support), controller based card detection / write protection is not
supported anymore by esdhc driver. Let's use GPIO for CD/WP on esdhc1
instead.
While at it, fix cd gpio polarity for esdhc2. This is wrong and
currently only works because the imx esdhc driver ignores the polarity.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Move the display {} node out of the soc {} node . This just aligns
the DT with other boards, there is no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Currently the __field() macro in TRACE_EVENT is only good for primitive
values, such as integers and pointers, but it fails on complex data types
such as structures or unions. This is because the __field() macro
determines if the variable is signed or not with the test of:
(((type)(-1)) < (type)1)
Unfortunately, that fails when type is a structure.
Since trace events should support structures as fields a new macro
is created for such a case called __field_struct() which acts exactly
the same as __field() does but it does not do the signed type check
and just uses a constant false for that answer.
Cc: Tony Luck <tony.luck@gmail.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
syscall_regfunc() ignores the kernel threads because "it has no effect",
see cc3b13c1 "Don't trace kernel thread syscalls" which added this check.
However, this means that a user-space task spawned by call_usermodehelper()
will run without TIF_SYSCALL_TRACEPOINT if sys_tracepoint_refcount != 0.
Remove this check. The unnecessary report from ret_from_fork path mentioned
by cc3b13c1 is no longer possible, see See commit fb45550d76 "make sure
that kernel_thread() callbacks call do_exit() themselves".
A kernel_thread() callback can only return and take the int_ret_from_sys_call
path after do_execve() succeeds, otherwise the kernel will crash. But in this
case it is no longer a kernel thread and thus is needs TIF_SYSCALL_TRACEPOINT.
Link: http://lkml.kernel.org/p/20140413185938.GD20668@redhat.com
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
1. Remove _irqsafe from syscall_regfunc/syscall_unregfunc,
read_lock(tasklist) doesn't need to disable irqs.
2. Change this code to avoid the deprecated do_each_thread()
and use for_each_process_thread() (stolen from the patch
from Frederic).
3. Change syscall_regfunc() to check PF_KTHREAD to skip
the kernel threads, ->mm != NULL is the common mistake.
Note: probably this check should be simply removed, needs
another patch.
[fweisbec@gmail.com: s/do_each_thread/for_each_process_thread/]
Link: http://lkml.kernel.org/p/20140413185918.GC20668@redhat.com
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
syscall_regfunc() and syscall_unregfunc() should set/clear
TIF_SYSCALL_TRACEPOINT system-wide, but do_each_thread() can race
with copy_process() and miss the new child which was not added to
the process/thread lists yet.
Change copy_process() to update the child's TIF_SYSCALL_TRACEPOINT
under tasklist.
Link: http://lkml.kernel.org/p/20140413185854.GB20668@redhat.com
Cc: stable@vger.kernel.org # 2.6.33
Fixes: a871bd33a6 "tracing: Add syscall tracepoints"
Acked-by: Frederic Weisbecker <fweisbec@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
The "port" node was misplaced in the original patch, therefore making
the LCD dysfunctional on this board. Fix this by moving the "port" DT
node into the "display {}" node.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Using the generic function saves looking up this custom one in a source
navigator.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Link: https://lkml.kernel.org/r/1401894112-13386-1-git-send-email-daniel.thompson@linaro.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The driver was configuring the interrupt handler for the Level-2
interrupts to be "level" triggered while they are in fact "edge"
triggered. Fix this by using the correct handler.
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lkml.kernel.org/r/1402337102-19428-1-git-send-email-f.fainelli@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Currently, the thermal quirk is skipped only if the SoC revision is known to be
one that does not need them, but if the SoC revision cannot be obtained, the
quirk is applied assuming it's needed.
However, this quirk must be applied only we are sure the SoC needs it, for it
breaks the thermal support if applied on a SoC that doesn't need it. The reason
for this is that the quirk consists in changing the thermal devicetree
compatible string and register offsets, to workaround a hardware bug in the
early SoC revision.
Such changes are wrong if the SoC is a new revision and doesn't need
the workaround. Therefore, this commit changes the behavior, by
requiring the SoC revision to be known in order to peform a quirk.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1402425283-24989-1-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Marvell has very recently released a public version of the "Functional
specifications" and "Hardware specifications" datasheets for the
Marvell Armada 370 SoC. This allows contributors and developers not
under NDA with Marvell to get more details about this SoC than what
the current kernel code shows, and hopefully allows to improve the
support for this SoC in the mainline kernel, as well as in other
projects.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402413878-20224-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Until now, the irq-armada-370-xp irqchip driver was not masking all
interrupts at initialization. While in most cases this is not a
problem because the bootloader has probably masked all interrupts, it
becomes a problem when you use kexec: you're in kernel A, with many
interrupts enabled, and then kexec into kernel B, without going
through the bootloader. So during the boot process, if an interrupt
occurs while the corresponding driver has not been loaded, you would
get spurious interrupts.
This commit fixes that by ensuring all interrupts are properly masked
when the irqchip driver is initialized. Note that interrupt masking
takes place at two level: at the global level (main_int_base) and at
the per-CPU level (per_cpu_int_base).
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit implements CPU hotplug support for the Marvell Armada XP
platform. The CPU hotplug stub functions from hotplug.c are moved into
platsmp.c, as it doesn't make much sense to have a separate file just
for these two functions.
In addition, this commit:
* Implements the ->cpu_die() function of SMP operations by calling
armada_370_xp_pmsu_idle_enter() to enter the deep idle state for
CPUs going offline.
* Implements a dummy ->cpu_kill() function, simply needed for the
kernel to know we have CPU hotplug support.
* The armada_xp_boot_secondary() function makes sure to wake up the
CPU if waiting in deep idle state by sending an IPI. This is
because armada_xp_boot_secondary() is now used in two different
situations: for the initial boot of secondary CPUs (where CPU reset
deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
is used to take CPU out of deep idle).
* At boot time, we exit from the idle state in the
->smp_secondary_init() hook.
This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The PMSU idle enter/exit functions will be needed for the CPU hotplug
implementation on Armada XP, so this commit removes their static
qualifier, and adds the appropriate prototypes in armada-370-xp.h.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The CPU hotplug code will need to call into PMSU functions to enter
and exit from deep idle states. However, the deep idle state is
currently entered by a function called do_armada_370_xp_cpu_suspend()
whose name really suggests it's an internal function, but we need to
export it to other files in mach-mvebu.
Therefore, this commit:
* Merges the code of do_armada_370_xp_cpu_suspend() into
armada_370_xp_pmsu_idle_prepare(), into a single function called
armada_370_xp_pmsu_idle_enter(), which prepares the PMSU for deep
idle, and then enters the deep idle state. This code will be common
to both cpuidle and CPU hotplug.
* For symetry, it renames the armada_370_xp_pmsu_idle_restore()
function to armada_370_xp_pmsu_idle_exit().
We also remove the 'noinline' qualifier for these functions, which
apparently had no reason to be here.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In preparation to the addition of CPU hotplug support for Armada XP,
and therefore moving the existing stub functions for hotplug support,
this commit removes the reference from the SMP implementation of
Armada 375/38x to the armada_xp_cpu_die() function. Proper CPU hotplug
support for Armada 375 and 38x will be implemented at a later point.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The mux2 node is missing the clock-output-names field that is required
by the clk-ppc-corenet driver.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
About a year ago I began taking patches, technically as Kumar's
assistant -- but since then all of the pull requests for this area have
come from me, and I've been doing most of the reviews. Update
MAINTAINERS to reflect this.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Virtualized environments may expose a e6500 dual-threaded core
as two single-threaded e6500 cores. Take advantage of this
and get rid of the tlb lock and the trap-causing tlbsx in
the htw miss handler by guarding with CPU_FTR_SMT, as it's
already being done in the bolted tlb1 miss handler.
As seen in the results below, measurements done with lmbench
random memory access latency test running under Freescale's
Embedded Hypervisor, there is a ~34% improvement.
Memory latencies in nanoseconds - smaller is better
(WARNING - may not be correct, check graphs)
----------------------------------------------------
Host Mhz L1 $ L2 $ Main mem Rand mem
--------- --- ---- ---- -------- --------
smt 1665 1.8020 13.2 83.0 1149.7
nosmt 1665 1.8020 13.2 83.0 758.1
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: commit message tweak]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Not involved in 8xx activities for years, update MAINTAINERS
to reflect it.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
T4240 has a third DMA engine controller, so add the corresponding DMA
node into the dts file.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: reword commit message]
Signed-off-by: Scott Wood <scottwood@freescale.com>
- remove CONFIG_RTC_DRV_CMOS in corenet32_smp_defconfig(it's unused),
reserve CONFIG_RTC_DRV_CMOS in mpc85xx_defconfig(needed on some CDS boards)
- enable CONFIG_RTC_DRV_DS1307, CONFIG_RTC_DRV_DS1374,
CONFIG_RTC_DRV_DS3232 in mpc85xx_defconfig, mpc85xx_smp_defconfig
- enable RTC support in corenet64_smp_defconfig
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Commit 82d86de25b "TLB lock recursive"
introduced a bug whereby cpu 0 uses the same value for "lock held" as
is used to indicate that the lock is free. This means that cpu 1 can
acquire the lock whenever it wants, regardless of whether cpu 0 has it
locked, which in turn means we can get duplicate TLB entries.
Add one to the CPU value to ensure we do not use zero as a "lock held"
value.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reported-by: Ed Swarthout <ed.swarthout@freescale.com>
Previously TID was being cleared before the tlbsx, but not after. This
can lead to a multiway hit between a TLB entry with TID=0 (previously
inserted when PID=0) and a TLB entry with TID!=0 that matches PID.
This can theoretically result in undefined behavior, though we probably
get lucky due to the details of the overlap. It also results in the
inability to use multihit detection to detect other conflicting TLB
entries, as well as poorer TLB utilization due to duplicating kernel
TLB entries.
Rather than try to patch up MAS1 after tlbsx, the entire value is
saved/restored as with MAS2.
I observed a slight improvement in TLB miss performance with this patch
applied.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reported-by: Ed Swarthout <ed.swarthout@freescale.com>
There is currently no DT binding for the CPLD which controls the LEDs
on the Net 2Big and Net 5Big. So use a platform device.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-2-git-send-email-andrew@lunn.ch
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
As Mainlining effort for SolidRun CuBox has been carried out on the
Engineering Sample, the board DTS was reflecting this. Actually,
SolidRun CuBox comes in three different variants:
Engineering Sample (ES), production with 1GB RAM (1G),
and production with 2GB RAM (2G).
Therefore, we base current dove-cubox.dts on to the 1G production
variant and add a ES dts to add required quirk for misrouted SDHCI
card detect on top of dove-cubox.dts. For the 2G variant we rely on
the bootloader to setup correct RAM size.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1401228006-3212-1-git-send-email-sebastian.hesselbarth@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
SolidRun is a company from Israel producing small-sized home-media
computers like the Marvell Dove based CuBox and Freescale IMX based
CuBox-i. Document the missing vendor prefix.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1401140009-31505-1-git-send-email-sebastian.hesselbarth@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Describe LaCie 2Big and 5Big Network v2 using device tree.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-3-git-send-email-andrew@lunn.ch
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Enable building LaCie 2Big and 5Big Network v2 in the mvebu v5 kernel.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-4-git-send-email-andrew@lunn.ch
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The armada_370_xp_pmsu_idle_prepare() function is only used internally
to pmsu.c, so there's no reason to not use the static qualifier.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401116474-31221-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On Marvell Armada platforms, the PMSU (Power Management Service Unit)
controls a number of power management related activities, needed for
things like suspend/resume, CPU hotplug, cpuidle or even simply SMP.
Since cpuidle support was added for Armada XP, the pmsu.c file in
arch/arm/mach-mvebu/ calls the cpu_suspend() and cpu_resume() ARM
functions, which are only available when
CONFIG_ARM_CPU_SUSPEND=y. Therefore, configurations that have
CONFIG_ARM_CPU_SUSPEND disabled due to PM_SLEEP being disabled no
longer build properly, due to undefined references to cpu_suspend()
and cpu_resume().
To fix this, this patch simply ensures CONFIG_ARM_CPU_SUSPEND is
always enabled for Marvell EBU v7 platforms. Doing things in a more
fine-grained way would require a lot of #ifdef-ery in pmsu.c to
isolate the parts that use cpu_suspend()/cpu_resume(), and those parts
would anyway have been needed as soon as either one of suspend/resume,
CPU hotplug or cpuidle was enabled.
Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402488397-31381-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
