- use macros instead of hard coded numbers for clock bindings
NOTE: this is based on v3.15-next/dt-samsung
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Merge tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung exynos clock related DT updates for v3.15 from Kukjim Kim:
- use macros instead of hard coded numbers for clock bindings
NOTE: this is based on v3.15-next/dt-samsung
* tag 'exynos-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: use macros in clock bindings for exynos5440
ARM: dts: use macros in clock bindings for exynos5420
ARM: dts: use macros in clock bindings for exynos5250
ARM: dts: use macros in clock bindings for exynos4
For exynos4412
- update vdd_arm voltage range for odroidx board
For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250
For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
support for arndale-octa board
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Merge tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung DT updates for v3.15 from Kukjin Kim:
For exynos4412
- update vdd_arm voltage range for odroidx board
For exynos5250
- add PMU sysreg node and update watchdog node
- re-organize RTC status
- add max77686 pmic node for smdk5250
For exynos5420
- add PMU sysreg, i2s, adma and watchdog nodes
- re-organize RTC status
- add fixed voltage regulators and regulator nodes
for smdk5420
- add PMIC, GPIO based wake up key and vmmc-supply
support for arndale-octa board
* tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Add vmmc-supply to MMC on arndale-octa board
ARM: dts: Add wake up key to arndale-octa board
ARM: dts: Add PMIC support to arndale-octa board
ARM: dts: Add fixed voltage regulators to smdk5420
ARM: dts: Add I2S nodes to exynos5420
ARM: dts: Add ADMA node to exynos5420
ARM: dts: Re-organize RTC status for exynos5250
ARM: dts: Re-organize RTC status for exynos5420
ARM: dts: Add regulator entries to smdk5420
ARM: dts: add max77686 pmic node for smdk5250
ARM: dts: update vdd_arm voltage range for exynos4412 based boards
ARM: dts: update watchdog device nodes for exynos5250 and exynos5420
ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
and a multi-purpose PHY in APM, all adapted to generic PHY framework.
Adapted USB3 PHY driver in OMAP to generic PHY driver and also used
the same driver for SATA in OMAP. It also includes miscellaneous cleanups
and fixes.
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Merge tag 'for_3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes:
Add new PHY drivers for SATA and USB in exynos, for USB in sunxi,
and a multi-purpose PHY in APM, all adapted to generic PHY framework.
Adapted USB3 PHY driver in OMAP to generic PHY driver and also used
the same driver for SATA in OMAP. It also includes miscellaneous cleanups
and fixes.
Make mcb depend on HAS_IOMEM and mcb-pci depend on PCI. This fixes build errors
discovered by the 0-day kernel build testing system.
Signed-off-by: Johannes Thumshirn <johannes.thumshirn@men.de>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
A scheduled scan is a more persistent setting and should take priority
over temporary regular scans. Abort the regular when a sched_scan
request arrives and then request the sched_scan.
The kernel API allows sending a sched_scan without canceling a regular
scan in progress, so this is our way to abstract the FW's limitations.
Make the scan-cancel Rx handler async and flush after invocation to
ensure new scans can't creep in before it.
Signed-off-by: Arik Nemtsov <arikx.nemtsov@intel.com>
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
cfg80211 assumes a scheduled scan is stopped synchronously. Wait for the
FW before returning to caller.
Don't do anything in the async handler in the stop-from-above flow.
There's no need to call the mac80211 sched-scan completion as the
cleanup will be automatic. Make sure the async handler is called before
the next incoming scan changes the scan_status by flushing the async
handlers after all invocations.
Signed-off-by: Arik Nemtsov <arikx.nemtsov@intel.com>
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Check for both cfg->d0i3 and fw d0i3 support in order
to enable d0i3 support.
Signed-off-by: Eliad Peller <eliadx.peller@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
BGN SKU won't scan on 5.2GHz obviously, but the firmware
still expects the driver to reserve space for the the probe
request for the 5.2GHz band.
Fix this by allocating space and leave it empty.
This fixes https://bugzilla.kernel.org/show_bug.cgi?id=69541
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
When indicating RF-kill toggle to the higher layer, that
may in turn call back to the transport (for MVM at least)
to turn off the device quickly. Instead of that, allow it
to return whether or not the device should be turned off,
this gets rid of the call indirection and will help make
the API more consistent when we go back to non-threaded
interrupts again for PCIe.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
1. Enable LP XTAL to avoid HW bug where device may consume much
power if FW is not loaded after device reset. LP XTAL is
disabled by default after device HW reset. Configure device's
"persistence" mode to avoid resetting XTAL again when SHRD_HW_RST
occurs in S3.
2. Add methods to access SHR (shared block memory space) directly from PCI
bus w/o need to power up MAC HW.
Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be
accessed directly from PCI bus through SHR arbiter even when MAC HW is
powered down. This is possible due to indirect read/write via
HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4)
registers.
Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
need not be powered up so no "grab inc access" is required.
For example, to read from SHR_APMG_GP1 register (0x1DC),
first, write to the control register:
HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
To write the register, first, write to the data register
HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
Signed-off-by: Alexander Bondar <alexander.bondar@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
When power update is initiated on BSS STA while P2P client
exists, the power command will be sent only on BSS STA vif
ignoring P2P client.
Since the firmware has symmetric constraints on the power
save enablement we can simplify the code a bit.
The current firmware doesn't know how to enable power
management on P2P client. Even BSS power management must
be disabled when a P2P client is added.
Future firmware will support power save on BSS and P2P client
as long as they are on different channels.
This was buggy since we didn't disable power management on
P2P client interface if BSS added on the same channel.
Signed-off-by: Avri Altman <avri.altman@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
As the antenna dependent fields depend on the firmware file and not
the NVM, use those fields in the VHT capability creation.
Additionally, fix the STBC and antenna pattern consistency fields.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
New firmware enforce valid values for the quota in D3.
The values given to the firmware when suspending and using
WoWLAN where dummy - change them to realistics values.
Tested-by: Luciano Coelho <luciano.coelho@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Switch pos to char * which makes the code a bit shorter
as well as other minor cleanups suggested by Joe Perches.
Signed-off-by: Eyal Shapira <eyalx.shapira@intel.com>
Reviewed-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
This message triggers on systems that don't support the API,
so suppress them when not debugging as it's not useful to
see it there.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Otherwise lockdep complains about the lock, I'm not sure
why we didn't see this before.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
The tlv320aic32x4 related lines were wrongly placed after tlv320aic3x lines.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
It is quite confusing to name the pointer to davinci_pcm_dma_params as
dma_data. Rename the pointer to avoid confusion.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The PCI part of the DesignWare I2C driver does a lot of things that are not
required anymore. For example drivers aren't supposed to handle PCI state
transitions themselves. This is all provided by the PCI bus core already.
In addition to that there is no point scheduling RPM suspend on driver's
idle hook but instead we can use RPM autosuspend for this (which is enabled
in the driver already).
As a bonus, this patch also fixes following compile warning which is
emitted when the driver was compiled without CONFIG_PM_RUNTIME set:
drivers/i2c/busses/i2c-designware-pcidrv.c:245:12: warning: ‘i2c_dw_pci_runtime_idle’ defined but not used [-Wunused-function]
Reported-by: xinhui.pan <xinhuix.pan@intel.com>
Reported-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This patch allows to set independantly SCL and SDA falling times.
The tLOW period is computed by taking into account the SCL falling time.
The tHIGH period is computed by taking into account the SDA falling time.
For instance in case the margin on tLOW is considered too small, it can
be increased by increasing the SCL falling time which is by default set
at 300ns.
The same applies for tHIGH period with the help of SDA falling time.
Signed-off-by: Romain Baeriswyl <romainba@abilis.com>
Reviewed-by: Christian Ruppert <christian.ruppert@abilis.com>
Acked-by: Shinya Kuribayashi <skuribay@pobox.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The reference clock path on newer IP FLLs requires a different
configuration, and should avoid integer mode operation. This patch adds
support for both the new encoding and updates the calculation.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Newer IP has an expanded encoding for the fratio bits. As the additional
used bits are unused on older IP simply expand the field to the new
size.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
No part of the FLL calculation depends on the value determined for the
gain but the gain does depend on other values. In preparation for future
updates this patch moves the gain to be the last thing calculated.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
OUTDIV will remain unchanged whilst the rest of the FLL configuration is
calculated so do this first.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
As we now calculate the FLL configuration at a later stage in the
process the fout member of the FLL structure will contain the desired
Fout frequency so no need to pass this in seperately.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Currently the FLL configuration is calculated before it is known which
FLL path the configuration will be applied to. Newer versions of the IP
have differences in the configuration required for each FLL path, which
makes it complicated to calculate the FLL configuration in advance.
This patch simply checks the validity of a requested input and output
frequency before we know which FLL path they will be applied to and
saves the actual calculation of the configuration until we know where
the settings will be applied.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Since we know in arizona_apply_fll if we are setting the sync or ref
path there is no need to set the outdiv seperately anymore. This patch
moves this from arizona_enable_fll to arizona_apply_fll.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Improve readability by adding defines for some of the constants
associated with FLL configuration.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
One is not a valid value for the OUTDIV start searching at 2 instead.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This fixes the following build errors when aic23 is configured as
module:
>> ERROR: "tlv320aic23_probe"
>> [sound/soc/codecs/snd-soc-tlv320aic23-i2c.ko] undefined!
>> ERROR: "tlv320aic23_regmap"
>> [sound/soc/codecs/snd-soc-tlv320aic23-i2c.ko] undefined!
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Put necessary SSYNC code into blackfin twi arch header. The generic TWI
driver should not contain any architecture specific code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The ADI TWI peripheral is not binding to the Blackfin processor only.
The bits macros and structs should be put in the generic include header.
And update head file path in drivers accordingly.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Move to the new style of defining the bus interfaces in separate modules
in order to simplify dependencies.
Signed-off-by: Mark Brown <broonie@linaro.org>
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.
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Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Merge OMAP crossbar support from Tony Lindgren:
Add support for GIC crossbar that routes interrupts on newer omaps.
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.
* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA: Enable Crossbar IP support for DRA7XX
ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu watchdog driver changes for v3.15 (incremental #2)
- remove warnings by using %pa for phys_addr_t
* tag 'mvebu-watchdog-3.15-2' of git://git.infradead.org/linux-mvebu:
watchdog: orion_wdt: Use %pa to print 'phys_addr_t'
Signed-off-by: Olof Johansson <olof@lixom.net>
Some low-level optimizations and fixes that don't belong in an -rc
series for various OMAP-family chips, targeted for v3.15.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/prcm-a-for-v3.15/20140228124518/
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Merge tag 'omap-for-v3.15/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Power, reset and clock related changes via Paul Walmsley <paul@pwsan.com>, via
Tony Lindgren:
Some low-level optimizations and fixes that don't belong in an -rc
series for various OMAP-family chips, targeted for v3.15.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/prcm-a-for-v3.15/20140228124518/
* tag 'omap-for-v3.15/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP3+: DPLL: stop reparenting to same parent if already done
ARM: OMAP2+: clock: fix rate prints
ARM: AM43x: hwmod data: register spinlock OCP interface
ARM: OMAP2+: clockdomain: Reintroduce SW_SLEEP Support
ARM: OMAP2+: AM43xx: implement support for machine restart
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY.
This is the physical layer interface for the corresponding host
controller. Currently, only external clock and Gen3 SATA mode
are supported.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
The OMAP_USB2 and OMAP_PIPE3 PHY devices will not be
detected if the OMAP_OCP2SCP bus driver is not present.
Make them depend on it.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded
workaround to issue a softreset to the SATA controller doesn't seem to
work. Here we just prevent SATA DPLL from Idling and hence avoid
the issue altogether.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Limit .power_on() and .power_off() to just control the
PHY power and not the DPLL. The DPLL will be enabled
in .init() and idled in .exit().
Don't reprogram the DPLL if it has been already locked
by the bootloader. This fixes a problem with SATA, where
it fails if SATA was used by the bootloader.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
SATA PHY doesn't need 'wkupclk; and 'refclk' so don't
try to get them for SATA PHY.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
