Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This adds the common dpm (dynamic power management)
infrastructure:
- dpm callbacks
- dpm init/fini/suspend/resume
- dpm power state selection
No device specific code is enabled yet.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Has a different dpm controller than r600.
v2: rebase on gpu reset changes
v3: rebase on get_xclk changes
v4: update rptr/wtpr callbacks
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
dpm needs access to atombios data and command tables
for setup and calculation of a number of parameters.
v2: endian fix
v3: fix mc reg table bug
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This is required for certain advanced functionality.
v2: save/restore list takes dword offsets
v3: rebase on gpu reset changes
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Since commit ab78029 (drivers/pinctrl: grab default handles from
device core), we can rely on device core for handling pinctrl.
So remove devm_pinctrl_get_select_default() from the driver.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
v2: fix up for latest reset changes
v3: use CP for pt updates for now
v4: update for 2 level PTs
v5: update for ib_parse removal
v6: vm_flush api change
v7: rebase
v8: fix gfx ring function pointers
v9: fix vm_set_page function params
v10: update for compute changes
v11: cleanup for release
v12: update rptr/wptr callbacks
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The compute rings use RELEASE_MEM rather then EOP
packets for writing fences and there is no SYNC_PFP_ME
packet on the compute rings.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Type 2 packets are deprecated on CIK MEC and we should use
type 3 nop packets. Setting the count field to the max value
(0x3fff) indicates that only one dword should be skipped
like a type 2 packet.
v2: add comment to code
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
On CIK, the compute rings work slightly differently than
on previous asics, however the basic concepts are the same.
The main differences:
- New MEC engines for compute queues
- Multiple queues per MEC:
- CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues
- KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues
- Queues can be allocated and scheduled by another queue
- New doorbell aperture allows you to assign space in the aperture
for the wptr which allows for userspace access to queues
v2: add wptr shadow, fix eop setup
v3: fix comment
v4: switch to new callback method
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
The doorbell aperture is a PCI BAR whose pages can be
mapped to compute resources for things like wptrs
for userspace queues.
This patch maps the BAR and sets up a simple allocator
to allocate pages from the BAR.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add callbacks to the radeon_asic struct to handle
rptr/wptr fetchs and wptr updates.
We currently use one version for all rings, but this
allows us to override with a ring specific versions.
Needed for compute rings on CIK.
v2: udpate as per Christian's comments
v3: fix some rebase cruft
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
With the new eMMC5.1 spec, there is a new EXT_CSD register with
the revision number(EXT_CSD_REV) 7. This patch updates the check
for ext-csd.rev number as 7.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
With device core now able to setup the default pin configuration, the
call to devm_pinctrl_get_select_default can be removed. And the pin
configuration code based on the deprecated Samsung specific gpio
bindings is also removed.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Instead of parsing the DT binding on our own, use the standard parser
mmc_of_parse(), introduced by commit 6c56e7a.
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Chris Ball <cjb@laptop.org>
In addition to just logging errors encountered during DT parsing or
allocating GPIO slots for CD/WP, mmc_of_parse() now returns with an error.
In particular, this is needed if the GPIO allocation may return
EPROBE_DEFER.
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
In preparation to switching the jz4740 clk driver to the
common clk framework, update the clk enable/disable calls
to clk_prepare_enable/clk_disable_unprepare.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
of_match_ptr() eliminates having an #ifdef returning NULL for the case
when OF is disabled.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
As there are no more users of the flexcan platform file, let's remove it.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Instead of using a GPIO to turn on/off the CAN transceiver, it is better to
use a regulator as some systems may use a PMIC to power the CAN transceiver.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
As there are no imx in-tree users of flexcan_platform_data, this patch removes
the possibility to register a flexcan device with platform data.
The functionality to swith on/off CAN transceivers is added to DT via
regulators in a later patch.
Compile time tested with imx_v4_v5_defconfig and imx_v6_v7_defconfig.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This patch set updates da850 DTS files to enable use of
C pre-processor. Also updates pinctrl-single DT data
to go with changes done in that module to enable a
single register to service configuration of multiple
pins.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRyzY7AAoJEGFBu2jqvgRNsZsP/05zTYOFWNm0EbchMh1HgFkw
2oXJG+i8SoC/lm9cW8Lad1fRHANMs2fYdKScH0t838wCH1ldfovFWTSHym9U5tp+
bh8rPV8On9dhPsTcXCNzgt4CE4BJ2FTHUfgdQITifyu84hDYmC67XFF+MdfHo8sU
J+HoVg3595Uv0m62UfPvzPUfEG/ckeigB2M8OeN3T8hVFccNp5KB1/od5AtB1qgk
6OAsahD02S1oTaAOLMdkYV/7M665r351PC+MjMJWuV0ee55lVViqBG+jMn0O+Hx5
IxkcDFLrp+V7Z9WXqH/NC9A9hJmx1n9nrRRUydbDmWeHkQOKUN5r8VAA7q5O/QSy
VCEhxvEnJd1oNZqpfxLTZLX71OqjC1bMNKX5x+nVwLA7EKJ4r0ZA9vzGeS+D6Ca3
ds+fP/k8NrP+xt1vecR4kCwOCg7eLYC+9LQHtLiTe55BkD54IUx58JqKZ1DiePK8
4uPGoBGvgNBk2ZF9EvrlloNrxeSsgbk2n3EkgVv9NYJ1V1e/T8bUSrBk7MGCgJmv
HQwlCPgU4qbw6KqszTEv3b3gSOx8XfR89g8w6GM50XuIonknx6QybCOhxhnYfKei
Rk9C5BKcW5IUd9PowwiNV5NMga4Yaw1nZHb1SIKrRfi4McSa47aq9reo0IX+lCyd
yz3MtBHOrkshgscnFgMz
=RU+m
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.11/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/late
From Sekhar Nori:
Device Tree updates for DaVinci
This patch set updates da850 DTS files to enable use of
C pre-processor. Also updates pinctrl-single DT data
to go with changes done in that module to enable a
single register to service configuration of multiple
pins.
* tag 'davinci-for-v3.11/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins
ARM: davinci: da850: Use #include for all device trees
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use standard PM state macros PCI_Dx instead of numeric 0/1/2..
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
- external irq on non-DT boards
- cpuidle code in some circumstances
- PMC code in relation with PLLB/PLL_UTMI/USB:
mainly for SAMA5D3 and AT91SAM9N12
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRyuyOAAoJEAf03oE53VmQDOgIALT6Ql8reZiaLcB9cuhpPVy1
vJAx8jxmJy0V1eXiD/Gl00261vb2tw7YJK9gt3zfLP0upqsYWrV5sV7f8UhR73RQ
rrJSfWfLkPFPBORYyKiHw9kWQUMBczybz9hhv3HbbxdVHmpD7LnaPRWXat71u1u/
Uh8UpF5d2s3lAE1BBqTr9Ec6n3r7vKqI/0MO2pWnyf11nfNZMI705zG9ehrQZHZx
v8hovwjWuQ/o06GD45xMJuunEp6IVHl01A2ZRcppuvQD4CtNBXo3AnlNLQ6TK7iz
9qOVhAiD8/1Td3CXSOOMiInCDBIVOXI/bbkKrAFJcTgGdL1jkAKEN3A1xUxXYVQ=
=28Xo
-----END PGP SIGNATURE-----
Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into next/fixes-non-critical
From Nicolas Ferre:
Several fixes for:
- external irq on non-DT boards
- cpuidle code in some circumstances
- PMC code in relation with PLLB/PLL_UTMI/USB:
mainly for SAMA5D3 and AT91SAM9N12
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/PMC: use at91_usb_rate() for UTMI PLL
ARM: at91/PMC: fix at91sam9n12 USB FS init
ARM: at91/PMC: at91sam9n12 family has a PLLB
ARM: at91/PMC: sama5d3 family doesn't have a PLLB
ARM: at91: cpuidle: Fix target_residency
ARM: at91: fix at91_extern_irq usage for non-dt boards
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This makes the l2x0 initialization fail gracefully on non-ux500
systems.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Sending the right snapshot context with each write is required for
snapshots to work. Due to the ordering of calls, the snapshot context
is never set for any requests. This causes writes to the current
version of the image to be reflected in all snapshots, which are
supposed to be read-only.
This happens because rbd_osd_req_format_write() sets the snapshot
context based on obj_request->img_request. At this point, however,
obj_request->img_request has not been set yet, to the snapshot context
is set to NULL. Fix this by moving rbd_img_obj_request_add(), which
sets obj_request->img_request, before the osd request formatting
calls.
This resolves:
http://tracker.ceph.com/issues/5465
Reported-by: Karol Jurak <karol.jurak@gmail.com>
Signed-off-by: Josh Durgin <josh.durgin@inktank.com>
Reviewed-by: Sage Weil <sage@inktank.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Select PINCTRL_TZ1090_PDC from SOC_TZ1090 to enable the PDC pin
controller driver once it is merged, and instantiate it from
tz1090.dtsi.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Grant Likely <grant.likely@linaro.org>
Select PINCTRL and PINCTRL_TZ1090 from SOC_TZ1090 to enable the main pin
controller driver once it is merged, and instantiate it from
tz1090.dtsi.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Grant Likely <grant.likely@linaro.org>
The cache configuration of the boot cpu is now duplicated to secondary
cpus, so there's no need to check for cache aliasing again when a
secondary cpu is booted. Therefore remove the check from
secondary_start_kernel().
Signed-off-by: James Hogan <james.hogan@imgtec.com>
If the cache and page size configuration allows for cache aliasing to
occur we warn on boot, but the log messages are easy to miss and will
result is random crashes occuring in userland. Let's panic too in this
case so that the user immediately knows they need to fix the cache
configuration or configured page size.
Also fix the warning messages which display the cache and page sizes to
include newlines, and add the word "Potential" since an actual cache
alias hasn't been detected.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Include *.dtsi files from *.dts using the preprocessor to set a good
example for future device tree files. Files included in the old way
don't get pre-processed.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Grant Likely <grant.likely@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Add symlink to include/dt-bindings from arch/metag/boot/dts/include/ to
match the one in arch/arm/... (see the commit below) so that
preprocessed device tree files can include various useful constant
definitions.
Commit c58299aa87 ("kbuild: create an
"include chroot" for DT bindings") merged in v3.10-rc1.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Grant Likely <grant.likely@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: linux-kbuild@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
