Now that the cpu update level is available the Atom PSE errata
check can use it directly without reading the MSR again.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
I got a request to make it easier to determine the microcode
update level on Intel CPUs. This patch adds a new "microcode"
field to /proc/cpuinfo.
The microcode level is also outputed on fatal machine checks
together with the other CPUID model information.
I removed the respective code from the microcode update driver,
it just reads the field from cpu_data. Also when the microcode
is updated it fills in the new values too.
I had to add a memory barrier to native_cpuid to prevent it
being optimized away when the result is not used.
This turns out to clean up further code which already got this
information manually. This is done in followon patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Link: http://lkml.kernel.org/r/1318466795-7393-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
As far as I can tell the only reason microblaze has
__ARCH_WANT_INTERRUPTS_ON_CTXSW is because it initializes new task state
with interrupts enabled so that on switch_to() interrupts get enabled.
So change copy_thread() to clear MSR_IE instead of set it, this will
ensure switch_to() will always keep IRQs disabled.
The scheduler will disable IRQs when taking rq->lock in schedule() and
enable IRQs in finish_lock_switch() after its done its magic.
This leaves ARM the only __ARCH_WANT_INTERRUPTS_ON_CTXSW user.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Add missing __ucmpdi2 helper function.
Error log:
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'
kernel/built-in.o: In function `print_graph_duration':
: undefined reference to `__ucmpdi2'
Based on MIPS code.
Signed-off-by: Michal Simek <monstr@monstr.eu>
It fixes the signal nr raised for divizion by zero from
SIGILL to SIGFPE, in accordance to POSIX and other archs.
This came up due to a failed test in the GCC testsuite.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Switch arch code to 189, the registered code in the upstream
version of binutils. Continue to accept the experimental 0xbaab.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Added support gor dma_direct_sync_single_for_*() and dma_direct_sync_sg_for_*()
Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
__dma_sync_page() was replaced by __dma_sync(), and parameters of calls to
the new function were adjusted to match __dma_sync()'s format.
Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
There is the problem with bit OR (|) because for
some combination is addr | size | addr+size equal
to seq.
For standard kernel setting (kernel starts at 0xC0000000)
is seq for user space 0xBFFFFFFF and everything below
this limit is fine.
But even address 0xBFFFFFFF is fine because it
is below kernel space.
Signed-off-by: Andrew Fedonczuk <andrew.fedonczuk@ericsson.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
Top bit is used as garbage and it must be clear
explicitly.
It is causing the problem with soft lookup code
because it checks delays which are long when
top bit is setup.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Add support for DiskOnChip G3 chips. The support is quite
limited yet :
- no flash writes/erases are implemented
- ECC fixes are not implemented
- powerdown is not implemented
- IPL handling is not yet done
On the brighter side, the chip reading does work.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Add support for EON spi flash EN25Q32B, which is not listed in id table,
need to add it in the id table to support the EON flash.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
This is similar to what the nbd driver does, among others.
Signed-off-by: Dan McGee <dpmcgee@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
Add ioctl to Freescale hypervisor management driver for 32-bit user-space
applications running on 64-bit guests.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for the msi-address-64 property of a PCI node. This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).
In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly. These fields are replace with a single field, msiir_offset,
to reflect the new meaning.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Since commit af337f3e63
"ARM: S3C2443: Move parts of the clock code to common clock file",
the init_clocks array is moved to arch/arm/plat-s3c24xx/s3c2443-clock.c.
Now we call s3c_register_clocks for init_clocks in s3c2443_common_init_clocks.
Thus we can remove the empty init_clocks array here and remove the
redundant s3c_register_clocks call for init_clocks in s3c2443_init_clocks.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S3C2443 uses hsmmc1 as its only hsmmc device and for S3C2416/S3C2450
it's the second hsmmc channel with the same PCLKCON bit.
The hsmmc-if clocks on both systems already got a devname, as did
the hsmmc pclk for hsmmc0 on the S3C2416. So to make it possible to
identify the hsmmc1 pclk on S3C2416 add the correct devname for it.
The sclk name on S3C2443 also is s3c-sdhci.1.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.
This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Cpufreq uses frequencies in kHz and not Hz, so set_rate and round_rate
would be called with a frequency of 266666000 instead of 266666666 but
the clock functions check for rates smaller or equal to the targetrate.
As the armdiv does not support steps this small we can accommodate
this by simply also setting the last 3 digits of the calculated rate
to zero.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The armdiv array may contain unset divider values.
Check the relevant value to prevent division by zero
errors. Also check for set nr_armdiv and armdivmask
before meddling with clkdiv0.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The system-layout of the armdiv and armclk is common to
S3C2443/S3C2416/S3C2450 and only differs in the array of
possible dividers. Therefore it is possible to reuse the
clock definitions for all of these SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is needed for making the armdiv clock common to S3C2443
and S3C2416/2450.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The S3C2416/2450 has only 3 bits for the armdiv setting instead
of the 4 bits of the S3C2443.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add voltage regulator and platform data definition for M-5MOLS sensor
and MIPI-CSI receiver drivers. Add CAM power domain dependencies for
FIMC device and set up camera port A GPIO. Configure I2C0 bus timings.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: HeungJun Kim <riverful.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables multi-format codec (MFC) support on ORIGEN board.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The ADC of the S3C2416/2450 SoC is 10 or 12 bit wide, has its
source selection in the register base+0x18 and its width
selection in bit 03 of the ADCCON register.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The S3C2443-adc is 10 bit wide and has its mux-select
in an extra register at base+0x18
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* 'for-linus' of git://oss.sgi.com/xfs/xfs:
xfs: revert to using a kthread for AIL pushing
xfs: force the log if we encounter pinned buffers in .iop_pushbuf
xfs: do not update xa_last_pushed_lsn for locked items
SFI tables reside in RAM and should not be modified once they are
written. Current code went to set pentry->irq to zero which causes
subsequent reads to fail with invalid SFI table checksum. This will
break kexec as the second kernel fails to validate SFI tables.
To fix this we use temporary variable for irq number.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
ftmac100 allocates a page per skb fragment. We must account
PAGE_SIZE increments on skb->truesize, not the actual frag length.
If frame is under 64 bytes, page is freed, so increase truesize only for
bigger frames.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
CC: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add a 'truesize' argument to niu_rx_skb_append(), filled with rcr_size
by the caller to properly account frag sizes in skb->truesize
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
vmxnet3 allocates a page per skb fragment. We must account
PAGE_SIZE increments on skb->truesize, not the actual frag length.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
CC: Shreyas Bhatewara <sbhatewara@vmware.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
ftgmac100 allocates a page per skb fragment. We must account
PAGE_SIZE increments on skb->truesize, not the actual frag length.
If frame is under 64 bytes, page is freed, and truesize adjusted.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
CC: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
that let us do local lock checks before requesting to the server.
Signed-off-by: Pavel Shilovsky <piastry@etersoft.ru>
Signed-off-by: Steve French <smfrench@gmail.com>
