A new test is added: caller_stack_write_tail_call tests that the live
stack is correctly tracked for a tail call.
Signed-off-by: Eduard Zingerman <eddyz87@gmail.com>
Signed-off-by: Martin Teichmann <martin.teichmann@xfel.eu>
Link: https://lore.kernel.org/r/20251119160355.1160932-5-martin.teichmann@xfel.eu
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This updates bpf_insn_successors() reflecting that control flow might
jump over the instructions between tail call and function exit, verifier
might assume that some writes to parent stack always happen, which is
not the case.
Signed-off-by: Eduard Zingerman <eddyz87@gmail.com>
Signed-off-by: Martin Teichmann <martin.teichmann@xfel.eu>
Link: https://lore.kernel.org/r/20251119160355.1160932-4-martin.teichmann@xfel.eu
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Three tests are added:
- invalidate_pkt_pointers_by_tail_call checks that one can use the
packet pointer after a tail call. This was originally possible
and also poses not problems, but was made impossible by 1a4607ffba.
- invalidate_pkt_pointers_by_static_tail_call tests a corner case
found by Eduard Zingerman during the discussion of the original fix,
which was broken in that fix.
- subprog_result_tail_call tests that precision propagation works
correctly across tail calls. This did not work before.
Signed-off-by: Martin Teichmann <martin.teichmann@xfel.eu>
Acked-by: Eduard Zingerman <eddyz87@gmail.com>
Link: https://lore.kernel.org/r/20251119160355.1160932-3-martin.teichmann@xfel.eu
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
A successful ebpf tail call does not return to the caller, but to the
caller-of-the-caller, often just finishing the ebpf program altogether.
Any restrictions that the verifier needs to take into account - notably
the fact that the tail call might have modified packet pointers - are to
be checked on the caller-of-the-caller. Checking it on the caller made
the verifier refuse perfectly fine programs that would use the packet
pointers after a tail call, which is no problem as this code is only
executed if the tail call was unsuccessful, i.e. nothing happened.
This patch simulates the behavior of a tail call in the verifier. A
conditional jump to the code after the tail call is added for the case
of an unsucessful tail call, and a return to the caller is simulated for
a successful tail call.
For the successful case we assume that the tail call returns an int,
as tail calls are currently only allowed in functions that return and
int. We always assume that the tail call modified the packet pointers,
as we do not know what the tail call did.
For the unsuccessful case we know nothing happened, so we do not need to
add new constraints.
This approach also allows to check other problems that may occur with
tail calls, namely we are now able to check that precision is properly
propagated into subprograms using tail calls, as well as checking the
live slots in such a subprogram.
Fixes: 1a4607ffba ("bpf: consider that tail calls invalidate packet pointers")
Link: https://lore.kernel.org/bpf/20251029105828.1488347-1-martin.teichmann@xfel.eu/
Signed-off-by: Martin Teichmann <martin.teichmann@xfel.eu>
Acked-by: Eduard Zingerman <eddyz87@gmail.com>
Link: https://lore.kernel.org/r/20251119160355.1160932-2-martin.teichmann@xfel.eu
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
In [1] Dan Carpenter reported that the following code makes the
Smatch static analyser unhappy:
17904 value = map->ops->map_lookup_elem(map, &i);
17905 if (!value)
17906 return -EINVAL;
--> 17907 items[i - start] = value->xlated_off;
The analyser assumes that the `value` variable may contain an error
and thus it should be properly checked before the dereference.
On practice this will never happen as array maps do not return
error values in map_lookup_elem, but to make the Smatch and other
possible analysers happy this patch adds a formal check.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/bpf/aR2BN1Ix--8tmVrN@stanley.mountain/ [1]
Fixes: 493d9e0d60 ("bpf, x86: add support for indirect jumps")
Signed-off-by: Anton Protopopov <a.s.protopopov@gmail.com>
Link: https://lore.kernel.org/r/20251119112517.1091793-1-a.s.protopopov@gmail.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
commit 603b441623 ("bpf: Update the bpf_prog_calc_tag to use SHA256")
changed digest of prog_tag to SHA256 but forgot to update tests
correspondingly. Fix it.
Fixes: 603b441623 ("bpf: Update the bpf_prog_calc_tag to use SHA256")
Signed-off-by: Xing Guo <higuoxing@gmail.com>
Link: https://lore.kernel.org/r/20251121061458.3145167-1-higuoxing@gmail.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Currently, test_perf_branches_no_hw() relies on the busy loop within
test_perf_branches_common() being slow enough to allow at least one
perf event sample tick to occur before starting to tear down the
backing perf event BPF program. With a relatively small fixed
iteration count of 1,000,000, this is not guaranteed on modern fast
CPUs, resulting in the test run to subsequently fail with the
following:
bpf_testmod.ko is already unloaded.
Loading bpf_testmod.ko...
Successfully loaded bpf_testmod.ko.
test_perf_branches_common:PASS:test_perf_branches_load 0 nsec
test_perf_branches_common:PASS:attach_perf_event 0 nsec
test_perf_branches_common:PASS:set_affinity 0 nsec
check_good_sample:PASS:output not valid 0 nsec
check_good_sample:PASS:read_branches_size 0 nsec
check_good_sample:PASS:read_branches_stack 0 nsec
check_good_sample:PASS:read_branches_stack 0 nsec
check_good_sample:PASS:read_branches_global 0 nsec
check_good_sample:PASS:read_branches_global 0 nsec
check_good_sample:PASS:read_branches_size 0 nsec
test_perf_branches_no_hw:PASS:perf_event_open 0 nsec
test_perf_branches_common:PASS:test_perf_branches_load 0 nsec
test_perf_branches_common:PASS:attach_perf_event 0 nsec
test_perf_branches_common:PASS:set_affinity 0 nsec
check_bad_sample:FAIL:output not valid no valid sample from prog
Summary: 0/1 PASSED, 0 SKIPPED, 1 FAILED
Successfully unloaded bpf_testmod.ko.
On a modern CPU (i.e. one with a 3.5 GHz clock rate), executing 1
million increments of a volatile integer can take significantly less
than 1 millisecond. If the spin loop and detachment of the perf event
BPF program elapses before the first 1 ms sampling interval elapses,
the perf event will never end up firing. Fix this by bumping the loop
iteration counter a little within test_perf_branches_common(), along
with ensuring adding another loop termination condition which is
directly influenced by the backing perf event BPF program
executing. Notably, a concious decision was made to not adjust the
sample_freq value as that is just not a reliable way to go about
fixing the problem. It effectively still leaves the race window open.
Fixes: 67306f84ca ("selftests/bpf: Add bpf_read_branch_records() selftest")
Signed-off-by: Matt Bobrowski <mattbobrowski@google.com>
Reviewed-by: Jiri Olsa <jolsa@kernel.org>
Link: https://lore.kernel.org/r/20251119143540.2911424-1-mattbobrowski@google.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Gracefully skip the test_perf_branches_hw subtest on platforms that
do not support LBR or require specialized perf event attributes
to enable branch sampling.
For example, AMD's Milan (Zen 3) supports BRS rather than traditional
LBR. This requires specific configurations (attr.type = PERF_TYPE_RAW,
attr.config = RETIRED_TAKEN_BRANCH_INSTRUCTIONS) that differ from the
generic setup used within this test. Notably, it also probably doesn't
hold much value to special case perf event configurations for selected
micro architectures.
Fixes: 67306f84ca ("selftests/bpf: Add bpf_read_branch_records() selftest")
Signed-off-by: Matt Bobrowski <mattbobrowski@google.com>
Acked-by: Song Liu <song@kernel.org>
Link: https://lore.kernel.org/r/20251120142059.2836181-1-mattbobrowski@google.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
arm64 JIT now supports gotox instruction and jumptables, so run tests in
verifier_gotox.c for arm64.
Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
Reviewed-by: Anton Protopopov <a.s.protopopov@gmail.com>
Link: https://lore.kernel.org/r/20251117130732.11107-4-puranjay@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Add support for a new instruction
BPF_JMP|BPF_X|BPF_JA, SRC=0, DST=Rx, off=0, imm=0
which does an indirect jump to a location stored in Rx. The register
Rx should have type PTR_TO_INSN. This new type assures that the Rx
register contains a value (or a range of values) loaded from a
correct jump table – map of type instruction array.
ARM64 JIT supports indirect jumps to all registers through the A64_BR()
macro, use it to implement this new instruction.
Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
Reviewed-by: Anton Protopopov <a.s.protopopov@gmail.com>
Acked-by: Xu Kuohai <xukuohai@huawei.com>
Link: https://lore.kernel.org/r/20251117130732.11107-3-puranjay@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Add support for the instructions array map type in the arm64 JIT by
calling bpf_prog_update_insn_ptrs() with the offsets that map
xlated_offset to the jited_offset in the final image. arm64 JIT already
has this offset array which was being used for
bpf_prog_fill_jited_linfo() and can be used directly for
bpf_prog_update_insn_ptrs.
Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
Reviewed-by: Anton Protopopov <a.s.protopopov@gmail.com>
Acked-by: Xu Kuohai <xukuohai@huawei.com>
Link: https://lore.kernel.org/r/20251117130732.11107-2-puranjay@kernel.org
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
AMD's SDCIAE forces all SDCI lines to be placed into the L3 cache portions
identified by the highest-supported L3_MASK_n register, where n is the maximum
supported CLOSID.
To support this, when io_alloc resctrl feature is enabled, reserve the highest
CLOSID exclusively for I/O allocation traffic making it no longer available for
general CPU cache allocation.
Introduce user interface to enable/disable io_alloc feature and encourage users
to enable io_alloc only when running workloads that can benefit from this
functionality. On enable, initialize the io_alloc CLOSID with all usable CBMs
across all the domains.
Since CLOSIDs are managed by resctrl fs, it is least invasive to make "io_alloc
is supported by maximum supported CLOSID" part of the initial resctrl fs
support for io_alloc. Take care to minimally (only in error messages) expose
this use of CLOSID for io_alloc to user space so that this is not required from
other architectures that may support io_alloc differently in the future.
When resctrl is mounted with "-o cdp" to enable code/data prioritization,
there are two L3 resources that can support I/O allocation: L3CODE and
L3DATA. From resctrl fs perspective the two resources share a CLOSID and
the architecture's available CLOSID are halved to support this.
The architecture's underlying CLOSID used by SDCIAE when CDP is enabled is the
CLOSID associated with the CDP_CODE resource, but from resctrl's perspective
there is only one CLOSID for both CDP_CODE and CDP_DATA. CDP_DATA is thus not
usable for general (CPU) cache allocation nor I/O allocation.
Keep the CDP_CODE and CDP_DATA I/O alloc status in sync to avoid any confusion
to user space. That is, enabling io_alloc on CDP_CODE does so on CDP_DATA and
vice-versa, and keep the I/O allocation CBMs of CDP_CODE and CDP_DATA in sync.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/c7d3037795e653e22b02d8fc73ca80d9b075031c.1762995456.git.babu.moger@amd.com
Introduce the "io_alloc" resctrl file to the "info" area of a cache resource,
for example /sys/fs/resctrl/info/L3/io_alloc. "io_alloc" indicates support for
the "io_alloc" feature that allows direct insertion of data from I/O
devices into the cache.
Restrict exposing support for "io_alloc" to the L3 resource that is the only
resource where this feature can be backed by AMD's L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE). With that, the "io_alloc" file is
only visible to user space if the L3 resource supports "io_alloc".
Doing so makes the file visible for all cache resources though, for example
also L2 cache (if it supports cache allocation). As a consequence, add
capability for file to report expected "enabled" and "disabled", as well as
"not supported".
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/e8b116a8f424128b227734bb1d433c14af478d90.1762995456.git.babu.moger@amd.com
Enable USB support for the 100ASK DshanPi A1 board.
Note that the HUSB311 Type-C chip is not supported.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://patch.msgid.link/20251120120011.279104-5-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The max-frequency property is already defined in the mmc
node of rk3576.dtsi. Remove the redundant definition.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/20251120120011.279104-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
"io_alloc" is the generic name of the new resctrl feature that enables system
software to configure the portion of cache allocated for I/O traffic. On AMD
systems, "io_alloc" resctrl feature is backed by AMD's L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE).
Introduce the architecture-specific functions that resctrl fs should call to
enable, disable, or check status of the "io_alloc" feature. Change SDCIAE state
by setting (to enable) or clearing (to disable) bit 1 of
MSR_IA32_L3_QOS_EXT_CFG on all logical processors within the cache domain.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/9e9070100c320eab5368e088a3642443dee95ed7.1762995456.git.babu.moger@amd.com
Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>:
The CAL_SET_STATUS and CAL_DATA_RB controls are volatile and read-only, but
the existing ASoC macros to define controls don't allow setting access
permissions, so those controls were marked as non-volatile read/write.
These four patches fix that.
The first two patches add two new control macros to soc.h. I really don't
like codec drivers open-coding a kcontrol_new content for a control that
will be managed by the ASoC info/get/put handlers. If a new type of ASoC
control definition is needed it's better to have it in soc.h so all the
dependencies between ASoC and the kcontrol_new content are in one place.
Merge series from Charles Keepax <ckeepax@opensource.cirrus.com>:
This series adds an initial SDCA class driver, this consists of a
primary driver attached to the SoundWire device, and auxiliary drivers
representing each of the functions of the SDCA device. These drivers all
use the APIs added over the past series's to provide the class
functionality, as such these final drivers themselves are quite thin.
Also a few fix ups at the start of the series that have gathered up
whilst the last SDCA series was in review.
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20251023204737.2716443-1-linus.walleij@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
AMD's SDCIAE (SDCI Allocation Enforcement) PQE feature enables system software
to control the portions of L3 cache used for direct insertion of data from I/O
devices into the L3 cache.
Introduce a generic resctrl cache resource property "io_alloc_capable" as the
first part of the new "io_alloc" resctrl feature that will support AMD's
SDCIAE. Any architecture can set a cache resource as "io_alloc_capable" if
a portion of the cache can be allocated for I/O traffic.
Set the "io_alloc_capable" property for the L3 cache resource on x86 (AMD)
systems that support SDCIAE.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/df85a9a6081674fd3ef6b4170920485512ce2ded.1762995456.git.babu.moger@amd.com
Add a kernel command-line parameter to enable or disable the exposure of
the L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) hardware
feature to resctrl.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/c623edf7cb369ba9da966de47d9f1b666778a40e.1762995456.git.babu.moger@amd.com
Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion
of data from I/O devices into the L3 cache. By directly caching data from I/O
devices rather than first storing the I/O data in DRAM, SDCI reduces demands on
DRAM bandwidth and reduces latency to the processor consuming the I/O data.
The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to
control the portion of the L3 cache used for SDCI.
When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
partitions identified by the highest-supported L3_MASK_n register, where n is
the maximum supported CLOSID.
Add CPUID feature bit that can be used to configure SDCIAE.
The SDCIAE feature details are documented in:
AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
Injection Allocation Enforcement (SDCIAE).
available at https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/83ca10d981c48e86df2c3ad9658bb3ba3544c763.1762995456.git.babu.moger@amd.com
Currently, RAPL PMU support requires adding CPU model entries to
arch/x86/events/rapl.c for each new generation. However, RAPL MSRs are
not architectural and require platform-specific customization, making
arch/x86 an inappropriate location for this functionality.
The powercap subsystem already handles RAPL functionality and is the
natural place to consolidate all RAPL features. The powercap RAPL
driver already includes PMU support for TPMI-based RAPL interfaces,
making it straightforward to extend this support to MSR-based RAPL
interfaces as well.
This consolidation eliminates the need to maintain RAPL support in
multiple subsystems and provides a unified approach for both TPMI and
MSR-based RAPL implementations.
The MSR-based PMU support includes the following updates:
1. Register MSR-based PMU support for the supported platforms
and unregister it when no online CPUs remain in the package.
2. Remove existing checks that restrict RAPL PMU support to TPMI-based
interfaces and extend the logic to allow MSR-based RAPL interfaces.
3. Define a CPU model list to determine which processors should
register RAPL PMU interface through the powercap driver for
MSR-based RAPL, excluding those that support TPMI interface.
This list prevents conflicts with existing arch/x86 PMU code
that already registers RAPL PMU for some processors. Add
Panther Lake & Wildcat Lake to the CPU models list.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Changelog edits ]
Link: https://patch.msgid.link/20251121000539.386069-3-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The current read_raw() implementation of the TPMI, MMIO and MSR
interfaces does not distinguish between atomic and non-atomic callers.
rapl_msr_read_raw() uses rdmsrq_safe_on_cpu(), which can sleep and
issue cross CPU calls. When MSR-based RAPL PMU support is enabled, PMU
event handlers can invoke this function from atomic context where
sleeping or rescheduling is not allowed. In atomic context, the caller
is already executing on the target CPU, so a direct rdmsrq() is
sufficient.
To support such usage, introduce an atomic flag to the read_raw()
interface to allow callers pass the context information. Modify the
common RAPL code to propagate this flag, and set the flag to reflect
the calling contexts.
Utilize the atomic flag in rapl_msr_read_raw() to perform direct MSR
read with rdmsrq() when running in atomic context, and a sanity check
to ensure target CPU matches the current CPU for such use cases.
The TPMI and MMIO implementations do not require special atomic
handling, so the flag is ignored in those paths.
This is a preparatory patch for adding MSR-based RAPL PMU support.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
[ rjw: Subject tweak ]
Link: https://patch.msgid.link/20251121000539.386069-2-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
driver, as well as the CEC extension to the DW-HDMI-QP driver.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmkZpqAQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgbqRCACrHGfhNyWP13LmjAHhClWMSC00oDDW7NAm
RYwDPAE/XHysIfEcHl+cnHK+kUCOtTmSqAUElCgML7g1Ix9LBkiNUdOYh7MVPyyK
AIZaXu2XH9YHIX9AzdgugyygHjFlvq9Uw4QnkSw50K35G5j+HcOFjwESlHvyqNHy
aCGhPaWj4yCHWcOD7mnKvh75QS33fhEnf+XAELB9aLS18rOQovXRZ1oGT0tlzfmC
kXbC8zFchqfb4zS4npZeS7A2kzZjqSu9JV7ZbXPzyvL0U7LjMh49hUVXrkU6icoQ
+jdNF/O8vICzsrvUkOCtwrSg04Ax95q68/pkWB9qRR5YOhwN1CUq
=LmM8
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzvsACgkQmmx57+YA
GNn0TRAAi5DjKimKa8J/zAFzYiRyp49z2vSZowQTBT8nzarnhMVm/ZqfSmzE+jmp
bl8EV4mrUYAiSedqnwzU8rEEwr0sFEcI5h1qri/aiRxrms5LWYsvcLpgwDk83fPo
l5LoQwN9IHa67LSXDwfEHRP4LLaJI/RK5KlZrgK5RITmaOs1Oc2N228PZIcHVROA
voYJ2Q44Y1BKvd86ABl0PK/fJppu0kr9whXWCqBVRXrI1n+fxUmr864aotCKm4W8
FDkImM4UTP5flaTCM3LNAwvPeymeJ5yD2m1VdwvdrGOeMntQMOic0yf5WrLO65sY
wi4825G3CSRxr+dlx1dl371urQ3IRmGgCQp8Ug70q0mim7LCMFEVQTL3A2RF8Jmq
iTNNwPX5J9/20m8Xr7nl4/Ktm3Ube96OzoQhjPwTpBJTIp+/mUDa1Qzdz2sprU3q
BLZGVzyufbU/OtBHJUb8KmnX8/vP7LbGhWuU79CwB4LdlgfjomWH4xngMxeew6Oq
We/bGc7bNCKZPrtaNG2wcYVQekLF0uKYQg9gePgQnyyyWTViBdB+fyStdKvzvbWF
vPHv5fCEO77hCoMv78obQVF3wiI9kB6/cqeOBIXCfbuqcIP0kH0ZeaZxxT0ZX+al
EUFeTxQh0SNGCfT/tE3nFl25SW1LRbsBdHgzB6MDXrl36/grcFc=
=qbBk
-----END PGP SIGNATURE-----
Merge tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/defconfig
Rockchip support for basic camera interface (CIF) and Synopsis DW-DP
driver, as well as the CEC extension to the DW-HDMI-QP driver.
* tag 'v6.19-rockchip-defconfig64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: defconfig: enable rockchip camera interface
arm64: defconfig: Enable DW HDMI QP CEC support
arm64: defconfig: Enable Rockchip extensions for Synopsys DW DP
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmkbiyIACgkQCx85Pw2Z
rcW+sg//cHW1pWhtaAnLTn9jNPmNz3fgQfCIspLFyMiahf2bzN0aM+AxQMFpkjsQ
xZ/ZB6GF9dVMnqhcfF1KyB/y45lRaMaS6aQ87sl7s9SOoUkrRQ4vd8lPZrRofCjx
nvF1Fdkv6R2LsngwWPJqAtusOi1RD8nWNVhEgRc7EJjNLYI7qKbv3E+2Lk8ESjcs
5dgcFXmEOFxW7LD7NNFge0QTPzaHE9eRTLnm1lq5bOwqobsJrtE0hSIzMG0ZyfLU
h5c8zi9f+V/WOjcWMQ2klON9/hKOQHnHNVjH6vcXQKOD8PG/K5cG14ow2A/oLART
/fFjTxHrFVPKMW8AjQdYB5+IdKCm2wyfOn+/VyT03y513e47eWf3lrc+bJCpfAu1
Kp5YTnbqIq3WolzVE9eIASkRlt20EWxtLayD+G72Wms6V1eZfaCrKemxtfysOIEI
TmXwG6zc1PrcM71R+TzxbR5fkKU0ad1wFZbJObYWuTCxUV2xZv/8DUrSTGGEHhOI
GWiFAEzjN83xVjPqvU2pxwYZ0cIoMNVP5mbZpfZ45Tre7RRNGDIBIw+e57MoHBrR
t7dls0+8KoKFEVODdjnzpEmb+2VRk3e1yeBwIyyT15KGPnhU96OrMTE+90apT+XS
WEV//YKdDTyiQMg8ol51/Jm5QnraOpkZUBcoRWNVkzVbdPuXho0=
=Updz
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzsoACgkQmmx57+YA
GNkB3hAAhJgmXYkUIuDR0nLayyu2SeOdiRSJ4xKm8RGq8XwDjOYCXsdxTuPZmASj
lQWuEIZ1fHGhFfDfH4yMPLMKqb7MkatTxG96W0D3hXTZtCmsuV6m82l5T3/4drvA
6gy3Y6f8dC7fkrKRgZcQbuZ3S5gYhmzqSmgNIxSv0NRkVRXxSEJaexvk1gRMThyG
QZ7ME3CBzQlNn+/ZJq3n3SNOGp0NgPEaTUF57cY/mP0uqljg4fS82KdIVOCuVzGe
hlCSDNnxM9jCXU47YWlyq9qu3LYyB/vB3BBoBs/6DtP0bNtBfJwujkTu96/5AKEt
uOIW2cVfwKu9FjPXv+HxXrCMmk7z+HkfPMeLrNKsdo9jV5ESuKnjtoFJAUXeziP/
hvM2jJAdp52TdKH9qaKWGbMVZeMkb17nXQKi2F2hhMXTsvccySOAycClULCExEuq
TIOgNzk7JtuK1bbxnRQLXQDbhNzzneEhvrwuT7MbeTl8sac+gmXmjreOocT3Ka88
v/QBiNPTf7qqtW82zCMUNLRl7P+GvqfejWB7VGipf8re1s9wOSiuPQemPkvsOi3m
qiQHCFa2fhSCYDa6uQ/cd1Dx6jdlEm/TpCNIrBPpOtEc9XhCROoG0RSq2seY7nOh
JJ2xL9rYBtOyYdRdUaQyJdq82PPOK0nw8YWUg1hgjQzSTxi9+a0=
=3pxp
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig
Qualcomm Arm64 defconfig updates for v6.19
Enable config options for the hardare used across Fairphone 3, 4, and 5.
Then enable Novatek display panels founds on Xiaomi Pocophone F1, and
the SM8750 MTP, eUSB2 PHY found in SM8750, NSS clock controller found in
IPQ5424, the SX150x gpio expander used in QCS615 reference device, and
the support for UFS inline crypto.
* tag 'qcom-arm64-defconfig-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable SX150x GPIO expander driver
arm64: defconfig: Build NSS clock controller driver for IPQ5424
arm64: defconfig: Enable SCSI UFS Crypto and Block Inline encryption drivers
arm64: defconfig: Add M31 eUSB2 PHY config
arm64: defconfig: Enable configs for Fairphone 3, 4, 5 smartphones
arm64: defconfig: Enable two Novatek display panels for MTP8750 and Tianma
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This update includes:
- CONFIG_MMC_SPI is set to module for at91_dt_defconfig
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCaRtHqAAKCRCejrg/N2X7
/SHYAQC7wLshtXYp+hl/yy3j9BRSoDCmpQLNP7IaOkXa/HyEpgD/VATNDNsXFsvc
ZbZH0oVbznx/q1by+5PuszyRmfgBbgM=
=jDaH
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgznMACgkQmmx57+YA
GNnPAA/+KqZvnvwA3xaSkwc0z4msi4VDj6+OkSLEqMTUtYYViEckrax87ZkvnOsv
EJZ0wvBvOHi3AGuBqOS8vQk6iQ79bfHYotQI6IGrNtKiSd0XJZcb+kQaXuhPXAt9
GR2BbZRizcc+C1YLlHCLiCVUsKJ9ileFQAb/893psVMY0x+Igk/7SjzzMpbp8UgU
zqUjaIFsWkLl60et+StNrs/q3getFNmPFXXCoA5ocG0GMfTPqy3l+w3xMoCKJnde
ydVgRPjY2U0PkqumuoGt2g3Z4sUm6UmUZYj1EwcR1fEzRQ23+ykXxBSQZDnFrrnW
1y1NabfyqxCRle1DFLb+8ypgPhRfM+bnVz2WM97FOVoAYsXce1/tn+W+Qmoxja8Q
jtvDkh8/Px0vSfpBZAuxbKCGNxEJyXCAJbfnF8mW1Vl+YmiAqQCt0qj6BTDUwy8L
mGz7X2ErqxPnhtDEyUTJgfPGMziRHr2Ga5qe+Cbxo6KBXeV009EkdwB/SZo0vnvt
8oOQu5Ag2DxREBAUoVOoBYibI6Mr/FQYw1gmEdqZp1OX9KD8GMvT5jC4sNunY8Ok
aWDGF3l1Ha0yJbrc8vUOvyF9zZaon5A/UFQ67Nk7aRGTDDrivJQQJnL7vCru5PI/
s6DV9RZfMrc4pwvgVWLz254Iktzdjc4M5Y6LYdb388dBqpnHRiM=
=W/Ld
-----END PGP SIGNATURE-----
Merge tag 'at91-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/defconfig
Microchip AT91 defconfig updates for v6.19
This update includes:
- CONFIG_MMC_SPI is set to module for at91_dt_defconfig
* tag 'at91-defconfig-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: at91_dt_defconfig: set MMC_SPI to module
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmkYPmwACgkQ3SOs138+
s6FUZg//WetHNSGE42IAnDE97FEP5K3IpFIgfMnZLkU9JPXQK8Maf+N1NSeUctbe
MP9cJ9napK1O+tNS8w0XDzrHJWTof/goMlRxDW91I99qh9+OIUVBt7SLyqkvbZEw
OrAZNLbl1NwDs5/67jL2UHWrdjVnzxJ9zfu3BJbqjwfV3FRCMIpdwXyiNUKplV7z
yr79JFlvWO71q6Vkqf/UdapRzDelU0EuwMaAeQJljCKdsse/yCRULo6zcFDxEGu1
GXnZybGzbM4PEEp3BwoMxG7ytx/DFLShgIbOmvvVkOsWySwQlqy1Eo+5bSmPUWA4
MbOocxyHKJMpuYU/ehKJqDF6jbpO0+zA+Td43Hz37PYzv/m93WHd+ZviKb0Wluyd
03nna5JhTzANiLY6HAw3mtxCm4Fv1FT/kGtQ6V4ZBa+kGgKBXjnS76haLoTklhbk
BfGzVvDp657J9rO7evctm7IulSJM80xeomuAAp9At7GrUajILkG389bLS5NDyBhR
NBWp0+hUtMMdQLkM5gNYxBjxjHvtRLRJtE6S//6BxyH+L9vaxBDbYdUB+8hz1uRG
iIafKaI+TLrtaLnIjG5zwdr20JqCdaVMoiCLVPFzSWcAxjT2GtpzlM+EWaEGMWtk
WVLDgUyDpRbiGHYxXHP5SWh79pul8mrzN4FdC3/McH4hpFp/zgg=
=tHXb
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzaUACgkQmmx57+YA
GNlANRAAuBST65pnIAXhPbgaPslfIovsLcNnenlP8p7Gyqwjtjlhp7KoIlqQ1MAN
KIjwaBZWEzo8YObHBTGW/tCbq242yT6TBs1q09UrqKwM7h9xoYEhRzqhHmrCyrKS
f6PeoTO4Xn3aZGF9dquRE5RWOqT37P8+745fKVYf2VlJ2qo63koavT53j6/hvLep
vnyM4kFYjr5WMMqGwwpamnlTiBTsXNHG8j/K+4SIT73616biDHr2xpFjQwuwAMJW
i0CdVTmWU1oPXY5YXNvXvtkCqHc8T0oY2eHnr4w8cuBp6agL1ygAOkQguVt6Jkse
5U8Glaq4yQdVOOuAMWEJMs5RCvt+aZru6BEm9cdtQDHCtWngk+VI+PypJM4Kp8x4
n93y8GToy0qoivUOJ/VToIp24foT7ko/PCf/nDuPYTF+9CEWrUW19sA/lI/eb35H
f0n4BzNg4jXuvySW0kdN0Oo12JAeaxEbrRg2UlrLwXoRUFzMEZjdbBCdHxbZOYsB
czaMFgvSya/QpaguP2lcMTBKArXYuiIYO1K3yvvqV5CiM5EbiOXWt1/+04lDZzhB
cpEpkhmdfbjDaaP2MKrgi/t8XJsvBe47HyPV8R+v5jFdi5kaneQ+ThGajmBy2b1f
ZZXw2HJqkcR3CeGOYdIr+qoN5I+nWxUCErDGUCAwmUZa2gj4AKM=
=RMkG
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
arm64: tegra: Default configuration changes for v6.19-rc1
Enable the new driver for the VRS PSEQ RTC found on Tegra234 and later.
* tag 'tegra-for-6.19-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: defconfig: Enable NVIDIA VRS PSEQ RTC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable ext4 by default on Tegra to restore systems booting from MMC.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmkYPHkACgkQ3SOs138+
s6EG7RAAwI1aJQEgDPLyHhOd5BVoUsxAvPqU8Kc+Futa5bnN33YKVmkj9PyElSjT
q+HPADbT4E/wBHkP6bDtdI2ySNZVYcLU80d1/2XjSZUvrIJ7umASX8bQqmRhNxZF
v9GNs2CfF5Fv+f8hI5fRfPYzBMaUk1Lj4HlAxl4bqHtkCS6q3QMP2QccdssegFGM
kiX+gv9xVOZmZ6Y7/mCdEZ6YJ4DKkxMFThCvFJZtP+NiRU9AIQY7zFTFvXsHgLEq
qhbk5tvoGi+edaH1vFEYK5wExb+cE4elxAHlZPDZWcrgAknnRE6gHVWzzuq97tgr
Bg+Ydp/LAWWfUk3naAz7SKJS2x2iuS6UYckRKN4r4icF7AtygM2hiap01WtbhLqq
O69my0ydkReVxyS4s6jgPPkwnoYL1D5ZLllNGripGZEkyF3SArq2EkF4I4NB5lzS
fH0m9nBcsxGCAavW2saXQclC2dlvMAUj8+xR68+lT6NR+E2wcTH52VzHg/IkUmIT
hwIa9Wo1ctU6To7m804Hb2TovNsOfKEYHCpO2n7wrwBb4X2egDZViI0742mzx2eX
mEOt4+4AdcdLOyGbaTZT0mSInCOG/OPIBioInpdlaFwUVKzYSnUgpWUjpyRi9AWj
Kk94QRGiRa41VBaxzPnfY6MlvaekuihKySx7exqzbNK7KqcMmXY=
=C4R/
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.19-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig
ARM: tegra: Default configuration changes for v6.19-rc1
Enable ext4 by default on Tegra to restore systems booting from MMC.
* tag 'tegra-for-6.19-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Enable EXT4 for Tegra
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaRMHjxsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeGzFAQC+GfbQfrl56jGrW02OCxNpjSzVwuTu
SYTlw5xwn9dwOQD9HPNqN8KPuCto81Rj/d7TZqzRhitLavhMYYBhS9GVhAY=
=0pZL
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzSMACgkQmmx57+YA
GNkPlQ/+K0fLkHkR4f6XvDyOXe4trgNFnG868jViY/4f4JfZCTCv8iScan2OT5w3
eDbVm/8YS7Uk5cRndWIiYibeR1DOGY0Ehm71Fmprl3n8if8JztWg5y0wENDeCE0e
BBDa5NiriyyQ7YTOiENY6AeeW5+9W3FRr/u9OuQ6BN+NHEPTml0AC+BdpVJxk0u+
oIYA+ccDoiqPn6U42vLiUzb2BCh+XLDaAXi7j+6WbIyCuJ1zvEpSbiwVYtKbhKLi
Qg6fgmMckLDon19EequoiABJSIwuoH+P7cOCBmb2/VGzV1680ovLvEqhZQPaOUoZ
ATWTLGCYRipkjBZfazIraYcUT4Ge8ZXhqB1N9t2DRh5zAq8xaWefylXu5OU3wowZ
r1RJ5kc/ysG9p5PC2kHPuf5Jmz4NTPM4CfUpzS38zUlRsPJU6hE8+No/tvnWttJ4
Tp0NJEBXqOJW58zN6B4XCrP7oStXLrZiic5ldMO+qG4ZXuLJplk1nDjVZOz2cava
JVs+ylWGUSycCzWpDs0xFXl9KVbtADTU8elTtpgN/uN+BchCtjkJEFex+CxnbPcU
RK/DeA3EBX1FYoJ76bEdNql9kT+LCb/w+54iPF3K9Zctp1E2TUCrI18EqXW6HAl3
m9uH+A7lNsFzVNvFTaAsGyHbcqG2EhCctsohd/Vf+5iz4jsix/U=
=d+Fg
-----END PGP SIGNATURE-----
Merge tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek defconfig updates
As MediaTek boards with UFS appeared some time ago, this adds a
single commit enabling the MediaTek UFS driver, allowing those
boards to boot over UFS as primary storage.
* tag 'mtk-defconfig-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable UFS support for MediaTek Genio 1200 EVK UFS board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable the Exynos ACPM clocks driver. Samsung Exynos platforms
implement ACPM to provide support for clock configuration, PMIC
and temperature sensors.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-5-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251110121344.120785-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaQSDwAAKCRCKwlD9ZEnx
cLmbAQDrw4g6TvLzEEuET5KvI9Bv/mKlSO3/dHc/Q8LRk3RWtAD6Ah3FatCWOXk8
ch65R/FOVxJbNkFsId8Pk2kk9CesYQw=
=XOpo
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgzJ0ACgkQmmx57+YA
GNkLRxAAt9oq5X2IdPFSh86rmhWA+SaWrbjYUzrH0Bd9QZaOx9ZkOdqN5GQ+w5hc
giC5SbT2BYbI0w9SdCwOoETY9cvhWwd1AkIm4KLQcTWFiA6LwcMV/Im/rEjGGt8H
Mp906arN53eimFAaCbYABwwffd+FGN7npqyX0IepULdl7rn70MevOJIs1BAW8Ymz
wCTeRbZqBohtP774a82AOyqy1Wk6Lb9ERC+lGdqzb3lkdBLsovWJYYBVvO0gbk9U
0uCau7cQHpcLTFNpltyQvazyvKKkWIVOWzhKsVSzpP+9xOXvyBxYaeq/VfPe09r0
IxcI+856slNnFnp8oggfcauQmj9UmFFX8QbVXkd+GfR0HMAQcSgRW13MNO+cec0R
RkhwHM58rPYx+f1Z6ZSBMvmd84mIgds3bXOSiEfs1Y2Tcic1BcTxp9qzdraQb04d
AWk1xlglb00C92Fw7zg+3+6aZQ/3JVXYj6CZlRVEZY83RqkPLLUWIFKxVvXdJRwv
QCqDmmWz3Z2jW+fHMfhV2ilMyxcv/YT8q31ioy3xuQB5nVOhKT4fxoWkAzKL0Qf1
M02JlN3q6zPO0S/jS6rm6NW1/5862P0t9xQb8iw+Vj1P+TW84V8K3TXBfBZLZvZV
LjDBLPSrv2pzyZ0++M1PxSlyxuQf41GlQYR5iXDSxnLFVVcT3O4=
=l7pQ
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/defconfig
Renesas ARM defconfig updates for v6.19
- Enable support for the Renesas RZ/G3S and RZ/G3E thermal drivers,
and the RZ/T2H and RZ/N2H ADC drivers in the ARM64 defconfig,
- Refresh the ARM SH-Mobile defconfig for v6.18-rc1.
* tag 'renesas-arm-defconfig-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: defconfig: Enable RZ/T2H / RZ/N2H ADC driver
ARM: shmobile: defconfig: Refresh for v6.18-rc1
arm64: defconfig: Enable the Renesas RZ/G3E thermal driver
arm64: defconfig: Enable Renesas RZ/G3S thermal driver
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The patch "7bd291abe2 sched: Unify the SCHED_{SMT,CLUSTER,MC} Kconfig"
has enabled the SCHED_MC/SCHED_SMT by default for arm64.
So remove the redundant code in defconfig.
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Huang Shijie <shijie@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20251021075704.527626-1-shijie@os.amperecomputing.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add bindings for the serial and timer peripherals, and a basic soc dtsi
for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board
for this SoC. Add myself as maintainer for this platform for the time
being.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaR7j/AAKCRB4tDGHoIJi
0k3VAP9GQl/z1wt5KBj+Qhcvo84KW0gAUZVnHn1limK2EkB29wD+Ix8MTs3FWoRT
HghtdGPQZBnrOdsuJe3lDieDt2Oxtgg=
=ZLUq
-----END PGP SIGNATURE-----
Merge tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc
Initial Anlogic Platform Support
Add bindings for the serial and timer peripherals, and a basic soc dtsi
for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board
for this SoC. Add myself as maintainer for this platform for the time
being.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: Setup support for Anlogic tree
riscv: defconfig: Enable Anlogic SoC
riscv: dts: anlogic: Add Milianke MLKPAI FS01 board
riscv: dts: Add initial Anlogic DR1V90 SoC device tree
riscv: Add Anlogic SoC famly Kconfig support
dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart
dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER
dt-bindings: riscv: Add Anlogic DR1V90
dt-bindings: riscv: Add Nuclei UX900 compatibles
dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
- initialize result before use in in error path
- fix uninitialized pointers with free attribute
-----BEGIN PGP SIGNATURE-----
iQJOBAABCgA4FiEE0qerISgy2SKkqO79Wr/6JGat8H4FAmka6uoaHGplbnMud2lr
bGFuZGVyQGxpbmFyby5vcmcACgkQWr/6JGat8H625hAAkeOfInc+UE3Y7KAuQ/o4
hbZE1wEQVJmCu1X7ugMowR7PWkntgOotUQPvGzgo8041UFpHCKSX+0y3yKud92yh
imiy7Gx9OxKYHUEC8J7SIuZpqJ2x87NPpLafA3+qLcYBAguY/aibpfhbDi9oi2qk
VZwisQuz5Gc5K2WJ5WUgj9Hxh9AlQQ6K8/oFl9QDZZv1H3GSYgiQJbVOJDVwjGir
4Ttm5b1NKMd8Jpa+sFkHOwQgOSvWujcUBRA+osopkz3JRRohgUrFQ+ShDc4/+ioe
NaQr6tJEiuBHihkSexPVyKRO7WyrIB/g33K5vB1GVwx/9MD8rWm/gU69jIMQn9PL
sNt6AMZx4A8MTL56slM9d9GYHQelFSS4alXgQW4C+iVzVcRMp0fiwDbxoe2Q7goy
MNX2Ic+ffYJJNkkBFye+udlmdH9Wqzz+NqIyb/9AEDx8TA1Fvl6sd19P+JedWH2q
dnbYVt4/N4l/8YJrh/T8/kJwvFheOC1Y5nlugf3wImcZgY3T9hhDOjYxMaCbZyCS
hcYzbylrMgzz2VP51xuClvI5OILKCA9fqR7nxVJo1a6fVTrT24jDELzE/hCkkPRS
Hra1yd/ZflIysuut7B8Yb2m0eSDhcyVtuf/kTFBndzduyxYq7Zza3J/UvrQUCHKy
0aACyNlFB4amfaRFfWHc21I=
=+IKZ
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgyywACgkQmmx57+YA
GNmIMw/9F1n6uAP0J0uVGLiDKSvxwN93oIYSoR3ToW/W4NUa67kJ/ScTO/ac+Mze
C2XAb4tY7rW3Ts34GWcW7G5sbV96HW8h81x9LsYGDdyNOzaLgESgvmsaObLH5RkY
K4DhgIyBTSpZf3QAqOd47BI2IkgHgcnjoyrCYMdC1b/wjrScwyvBxC7hbxS8Z4nu
mD2Cfdj/l41P09miemeLCXIcOHRJShtVRzZdszTmKqi3YEESAYSw57OKfE4flcuR
NhxLRwnZfetvuqW6wqNZBeoRLgTenpG5Qj2nPxJXpXG+gVw8EMvo87U/oq3bYNgu
+04EjN2Ulc3BPuupfq5K4x3Pmf0olkDJ/qyaeUc//R6ouwH/4hQvqRWUewhJ+1MF
wbfj/fPfOlhqPa5TiwwGWC9XK0ovq7bdcbEsVkJXJ7b4Do16zWa57dIS+heN4A/Z
UlXBvjEWgYd0H9+AGkWii3iFFy86FGRxflGYDfti6iRMeo3h+RbiNx3w8KbOgLg2
il6ne2TLvLg1pFqm67suPDXfyRRIKmkvIZtEyH8cdXmJ2zKYcrfoskd2Q9nd5bZE
Bzy0KrO18mXNTjcnd3ht+6hkYcAcQFetk6DgU7aKg0WDNOeWFPlnxr7BBASVSZjI
oiCcLW8GqCqJubMBjydso3q85AW8ig5phRCxuTP3kEbZPb71hMU=
=r+Hg
-----END PGP SIGNATURE-----
Merge tag 'qcomtee-fixes2-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into arm/fixes
QCOMTEE fixes2 for v6.18
- initialize result before use in in error path
- fix uninitialized pointers with free attribute
* tag 'qcomtee-fixes2-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee:
tee: qcomtee: initialize result before use in release worker
tee: qcomtee: fix uninitialized pointers with free attribute
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for the MT6582 SoC and its SMP bringup code.
This SoC is found in old smartphones and tablets from various
manufacturers.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaRL8NhsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMSwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeBsMAQDfPwcnCdt+K1Fe/WD8Fj+tGzooGWsM
HbYg3GwqpgXdVAEA+Nt7IED9janSdcFSq2qEjbH66koY1qhVtdWw4L3U0Ag=
=UmLF
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmkgyXsACgkQmmx57+YA
GNmulg/+NxNWh4hL5mo6E2pY/wnEekxM4wvIim8BQd8T7ylUhV/JeRBe8j5c2sWx
+z40okgH7NrPIphvwTsarSEKCnzeeWyI+0ESw+XAqyttq5KXQCLLDfe8ZlK8Osg5
L/q+2XhfzL3iHqkDTgfTINdDvxllvPX+Bc7V1tcWloEfy0pSz1JCLyTQa1VOpEIT
SVo0A0m2rrtR59RPm5XbU6FyTXc2LNKHMWiwQuQpdJyUQOi0ep9H0DN0P5q5ri8P
HZq3OqdhJAMAGvQ8HRyYGvjagII46OTkivPqwssy30PzQoqLEktLVqyAoBcSn1Js
HPAznkboddfT0HSjuyVWd34WP/lgW+106kf0Aq3JHhE0k+wZCGMtgFl3r5349a//
X111DBJ7dAbeo3/4YqLtoFsEflZKD3YasIb3Dii9FnicynQqf5JMa6MTazyua6vY
8c5YjCiSZ0h67EzYINWXmZjcImxdl8YfKiFO914lyt8D7nv6jQFLw44mHlIiI0Io
bTumOIRa1wZ2qmvZXpR5M716fqyH8WctHk4Rk8oWhZSl20lJEIpu6gzGTTWHpOnY
zVtBiN9ZcY8/feREZtSlEWUbC4RfNEKqC6PphmLenxaDfxKkaOscAqmX8MDvjw0G
RduLbdsC4SunR9I+lwKRgQndczRrwBM9uAkbMtSun6/7v4/d1es=
=HHJi
-----END PGP SIGNATURE-----
Merge tag 'mtk-arm32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/arm
MediaTek mach ARM32 updates
This adds support for the MT6582 SoC and its SMP bringup code.
This SoC is found in old smartphones and tablets from various
manufacturers.
* tag 'mtk-arm32-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
ARM: mediatek: add MT6582 smp bring up code
ARM: mediatek: add board_dt_compat entry for the MT6582 SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch series introduces platform support for Black Sesame Technologies
(BST) C1200 SoC and CDCU1.0 ADAS 4C2G board. BST is a leading automotive-grade
computing SoC provider focusing on intelligent driving, computer vision, and AI
capabilities for ADAS and autonomous driving applications. You can find more
information about the SoC and related boards at: https://bst.ai
This series provides the foundational platform enablement including device tree
bindings, SoC and board device trees, platform configuration, and maintainer
information. MMC/SDHCI driver support will be submitted in a separate patch series.
* bst/newsoc:
MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support
arm64: defconfig: enable BST platform support
arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board
arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs
dt-bindings: arm: add Black Sesame Technologies (bst) SoC
dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd.
Link: https://lore.kernel.org/all/20251016120558.2390960-1-yangzh0906@thundersoft.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add a MAINTAINERS entry for Black Sesame Technologies (BST) ARM SoC
support. This entry covers device tree bindings, drivers, and board files
for BST SoCs, and platform support.
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
