Add the iodomains node and reference the correct regulator for each
domain. This also includes adding the currently unused dvp regulators
and fixing up two regulators to follow the naming in the schematics.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The popmetal board was not included in the list of Rockchip boards,
so was only built when explicitly called with make rk3288-popmetal.dtb
but not in a generic make dtbs, so add the missing entry.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The Radxa Rock 2 Square board is a combination of the Radxa Rock 2 SoM
with the Square baseboard. Add a dtsi for the SoM which can be included
into the dts for the various baseboards (e.g. full and square) and a dts
for the square board.
Currently supported are serial console, wired networking, hdmi output,
eMMC and SD storage and USB.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add cap-sd-highspeed and cap-mmc-highspeed for rk3066a-bqcurie2
and rk3066a-rayeager boards to make sd cards run faster.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add cap-sd-highspeed and cap-mmc-highspeed for rk3188-radxarock
board to make sd cards running faster.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The pins for i2c5 can either be configured as "I2C5" which means that
they're controlled by the normal RK3288 I2C controller or as "EDP / HDMI
I2C". It's unclear why EDP is referenced here since apparently setting
the mux to this position enables I2C communication using the dw_hdmi
block with a patch like <https://patchwork.kernel.org/patch/7098101/>.
There appear to be some reasons why using the builtin I2C controller in
dw_hdmi is better than using the normal RK3288 I2C controller, so boards
based on rk3288 might eventually want to use this pinmux if it's known
to work.
Once driver support in dw_hdmi lands, boards would use this by selecting
this pinctrl for the HDMI block and then _not_ specifying a ddc-i2c-bus
and _not_ setting the status to "okay" for i2c5 (which uses the same
pins).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the previous patch ("rk3288: pull up cts lines") this is redundant,
I sent that patch for the same reason this existed here, so the lines don't
wiggle randomly when disconnected.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The flow control lines from a user accessible UART are optional,
the user might not have anything connected to those pins.
In order to prevent random interrupts happening and noise affecting
the cts pin should be pulled up.
Note that the default state for that pin on the rk3288 is pulled up,
so this patch merely restores them.
This is similar to what we're already doing with the RX pin,
so it should be safe. At worst it might be a slightly higher power usage
(through ~50 kohms) when the cts is low.
Suggested-by: Neil Hendin <nhendin@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
a.k.a. Haier Chromebook 11, and others
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This enables SDMMC0 on the board and gives a basic support for SD cards.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The timeout handling introduced in
7e2893a16d (nbd: Fix timeout detection)
introduces a race condition which may lead to killing of tasks that are
not in nbd context anymore. This was not observed or reproducable yet.
This patch adds locking to critical use of task_recv and task_send to
avoid killing tasks that already left the NBD thread functions. This
lock is only acquired if a timeout occures or the nbd device
starts/stops.
Reported-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Reviewed-by: Ben Hutchings <ben@decadent.org.uk>
Fixes: 7e2893a16d ("nbd: Fix timeout detection")
Signed-off-by: Jens Axboe <axboe@fb.com>
This reverts commit 5d250b0591.
It results on a deadlock on platforms where we need to (at least
partially) re-init hpd interrupts from power domain code, since
->hot_plug might again grab a power well reference (to do edid/dp_aux
transactions. At least chv is affected.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
References: http://mid.gmane.org/20151008133548.GX26517@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
When scaling_available_frequencies is read on an offlined cpu, then
either lockup or junk values are displayed. This is caused by
freed freq_table, which policy is using.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The Atmel sdhci device needs the
SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST quirk. Without it, the
internal clock could never stabilised when changing the sd clock
frequency.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock
Control Register to 0 before computing the new value and writing it.
It disables the internal clock which causes a reset mecanism. If we
write the new value before this reset mecanism is done, it will prevent
the stabilisation of the internal clock, so a delay is needed. This
delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is
used.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
With 64k pages, the next larger segment size is 512M. The linux
kernel also uses different protection flags to cover its code and data.
Because of this requirement, the vast majority of the kernel code and
data structures end up being mapped with 64k pages instead of the larger
pages common with a 4k page kernel.
Recent ARM processors support a contiguous bit in the
page tables which allows the a TLB to cover a range larger than a
single PTE if that range is mapped into physically contiguous
ram.
So, for the kernel its a good idea to set this flag. Some basic
micro benchmarks show it can significantly reduce the number of
L1 dTLB refills.
Add boot option to enable/disable CONT marking, as well as fix a
bug found by Steve Capper.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
[catalin.marinas@arm.com: remove CONFIG_ARM64_CONT_PTE altogether]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The kernel page dump utility needs to be aware of the CONT bit before
it will break up pages ranges for display.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The default page attributes for a PMD being broken should have the CONT bit
set. Create a new definition for an early boot range of PTE's that are
contiguous.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add the supporting macros to check if the contiguous bit
is set, set the bit, or clear it in a PTE entry.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Define the bit positions in the PTE and PMD for the
contiguous bit.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add the number of pages required to form a contiguous range,
as well as some supporting constants.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In case of armada_38x_quirks error, all clocks should be cleaned-up, same
as after mv_conf_mbus_windows failure.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Cc: <stable@vger.kernel.org> # v4.2
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
According to 'FE-2946959' erratum the clock inversion option is
needed to support slow frequencies when the card input hold time
requirement is high. This setting is not required for high speed
MMC and might cause timing violation.
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Cc: <stable@vger.kernel.org> # v4.2
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
shci-pxav3 driver is enabling by default the
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN quirk. However this quirk is not
required for Armada 38x and leads to wrong clock setting in the divider.
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Cc: <stable@vger.kernel.org> # v4.2
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Now that we have introduced the core fns we should make hda use these
helpers
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
The current codec helpers are local to hda code and needs to be moved to
core so that other users can use it.
The helpers to read/write the codec and to check the
power state of widgets is copied
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Use the port->name string which we previously formatted when referring to
the name of a port, rather than manually creating the port name each time.
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
If we have a missing required property, report the full node name rather
than a vague "PCIe DT node" statement. This allows the exact node in error
to be identified immediately.
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Rather than using for_each_child_of_node() and testing each child's
availability, use the for_each_available_child_of_node() helper instead.
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Rather than open-coding of_get_available_child_count(), use the provided
helper instead.
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The idea that you can arbitarily read 32-bits from PCI configuration space,
modify a sub-field (like the command register) and write it back without
consequence is deeply flawed.
Status registers (such as the status register, PCIe device status register,
etc) contain status bits which are read, write-one-to-clear.
What this means is that reading 32-bits from the command register,
modifying the command register, and then writing it back has the effect of
clearing any status bits that were indicating at that time. Same for the
PCIe device control register clearing bits in the PCIe device status
register.
Since the Armada chips support byte, 16-bit and 32-bit accesses to the
registers (unless otherwise stated) and the PCI configuration data register
does not specify otherwise, it seems logical that the chip can indeed
generate the proper configuration access cycles down to byte level.
Testing with an ASM1062 PCIe to SATA mini-PCIe card on Armada 388. PCIe
capability at 0x80, DevCtl at 0x88, DevSta at 0x8a.
Before:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - Write DevCtl only
/# setpci -s 1:0.0 0x88.l - CorrErr cleared - FAIL
00002810
After:
/# setpci -s 1:0.0 0x88.l - DevSta: CorrErr+
00012810
/# setpci -s 1:0.0 0x88.w=0x2810 - check DevCtl only write
/# setpci -s 1:0.0 0x88.l - CorErr remains set
00012810
/# setpci -s 1:0.0 0x88.w=0x281f - check DevCtl write works
/# setpci -s 1:0.0 0x88.l - devctl field updated
0001281f
/# setpci -s 1:0.0 0x8a.w=0xffff - clear DevSta
/# setpci -s 1:0.0 0x88.l - CorrErr now cleared
0000281f
/# setpci -s 1:0.0 0x88.w=0x2810 - restore DevCtl
/# setpci -s 1:0.0 0x88.l - check
00002810
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
PCI requires reads to reserved or unimplemented configuration space to
return zero and complete normally (see PCI r3.0, sec 6.1). However, the
root port software implementation was returning 0xfffffff and
PCIBIOS_BAD_REGISTER_NUMBER.
Return zero when reading reserved or unimplemented config space.
[bhelgaas: changelog]
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> (Armada XP GP)
Tested-by: Andrew Lunn <andrew@lunn.ch> (Kirkwood DIR665)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
For some reason, only the little-endian flavor of
powerpc provided the zero_bytemask() implementation.
Reported-by: Michal Sojka <sojkam1@fel.cvut.cz>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
- properly get the slow clock from timer-atmel-st, tcb_clksrc and pwm-atmel-tcb
- small fix in an error path for tcb_clksrc
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Merge tag 'at91-cleanup-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/drivers
Merge "First batch of cleanups for 4.4:" from Alexandre Belloni:
- properly get the slow clock from timer-atmel-st, tcb_clksrc and pwm-atmel-tcb
- small fix in an error path for tcb_clksrc
* tag 'at91-cleanup-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
misc: atmel_tclib: get and use slow clock
clocksource: tcb_clksrc: fix setup_clkevents error path
clocksource: atmel-st: get and use slow clock
If the bus is being configured with a bus-range that does not start at
zero, pass that starting bus number to pci_scan_root_bus(). Passing the
incorrect value of zero causes attempted config accesses outside of the
supported range, which cascades to an OOPs spew and eventual kernel panic.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>
DaVinci clock code. And a fix to use a more appropiate
format specifier in a debug message.
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Merge tag 'davinci-for-v4.4/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/fixes-non-critical
Merge "DaVinci non-critical fixes for v4.4" from Sekhar Nori:
Fix for incorrect handling of NULL clk pointer in
DaVinci clock code. And a fix to use a more appropiate
format specifier in a debug message.
* tag 'davinci-for-v4.4/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: clock: Correct return values for API functions
ARM: davinci: re-use %*ph specifier
Tronfy is an emerging brand in China specializing in Home Theater
solutions for the normal consumers.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Add missing CPG/MSTP Clock Domain for sound on r8a779[01] SoCs
* Tidy up SCI resource region on r8a779[018] SoCs
* Add pinmux for iic0 on Lager board
* Use CCF for audio clock on Lager and Koelsch boards
* Use serial0 and 1 as serial ports on Marzen board
* Use adxl345-specific compatible property for KZM9G board
* Document compat string for Silk board
* Enable GPIO, I2C, PCI, QSPI, USB PHY and HS, and VIN support on r8a7794/Silk
* Add initial support for r8a7791/porter
* Add common file for AA121TD01 panel
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Merge tag 'renesas-dt-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Renesas ARM Based SoC DT Updates for v4.4" from Simon Horman:
* Add missing CPG/MSTP Clock Domain for sound on r8a779[01] SoCs
* Tidy up SCI resource region on r8a779[018] SoCs
* Add pinmux for iic0 on Lager board
* Use CCF for audio clock on Lager and Koelsch boards
* Use serial0 and 1 as serial ports on Marzen board
* Use adxl345-specific compatible property for KZM9G board
* Document compat string for Silk board
* Enable GPIO, I2C, PCI, QSPI, USB PHY and HS, and VIN support on r8a7794/Silk
* Add initial support for r8a7791/porter
* Add common file for AA121TD01 panel
* tag 'renesas-dt-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (28 commits)
ARM: shmobile: porter: add Ether DT support
ARM: shmobile: fix SILK board name
ARM: shmobile: r8a7794: add HS-USB DT support
ARM: shmobile: dts: Add common file for AA121TD01 panel
ARM: shmobile: r8a7794: link PCI USB devices to USB PHY
ARM: shmobile: silk: enable USB PHY
ARM: shmobile: r8a7794: add USB PHY DT support
ARM: shmobile: porter: initial device tree
ARM: shmobile: add Porter board DT bindings
ARM: shmobile: silk: enable internal PCI
ARM: shmobile: r8a7794: add internal PCI bridge nodes
ARM: shmobile: r8a7790: lager: add pinmux for iic0
ARM: shmobile: r8a7778: tidyup SSI resource region
ARM: shmobile: r8a7791: tidyup SSI resource region
ARM: shmobile: r8a7790: tidyup SSI resource region
ARM: shmobile: lager: use CCF for audio clock
ARM: shmobile: koelsch: use CCF for audio clock
ARM: shmobile: silk: add VIN0/ADV7180 DT support
ARM: shmobile: r8a7794: add VIN DT support
ARM: shmobile: silk: add I2C1 DT support
...
The generic driver kept a global struct pci_ops ("gen_pci_ops") which it
patched with the .map_bus() method appropriate for the bus device. This is
a problem when we have two different types of bus devices: the .map_bus()
method for the last device probed clobbers the method for previous devices.
The result is that only the last bus device probed has the correct
.map_bus(), and the others fail.
Move the struct pci_ops into the bus-specific structure and initialize a
pointer to it when the bus device is probed.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Will Deacon <will.deacon@arm.com>
