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1,089,026 commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Arnd Bergmann
|
ab930ecfce |
Samsung clock controller changes for v5.18
Add support for Tesla FSD SoC clock controller within Samsung Exynos SoC clock controller drivers. The Tesla FSD's clock controller is similar to Samsung Exynos one, so entire driver structure can be re-used. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH9RtIQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD10PbD/0crt0yMU7CG/AzPci7HnlFWtSv8o2E3SIr p1i78nyN4JxXkJ6+mNFtgHKnZThdqh5MbKN8pTOnaBD0LBeNYYcHRMc4AKNdoIdL OggqqpfA5+5OhVdirTOKUWGaqqO7/jKWkSpAb8jDC0QBp4k7VKoUDnSdegwEb6hf oAC4JRVNEKpbyTXHoHwmMAoZOIpLvEpv+ZRV0JPRBx80FABiRCA6ee9zKpOVF1LC i8ioioqbzZmRdKOtUmKi6nP0eLhJFFjSk49PSgBXF9RJKu+A+EortAtgOVWd/x9O V0Qmaa/LRL/EbzQyYF6zU2xcoAEK6kRcOZ4PX8Yh/M4jz9VxDRlNhvHYwNzKfXuz P2ZNz5EnVDOYwEFzMdsHQV5mm1xK08zrA9O+BZwkVV3LqNNk1ANcEIP2/DIHOTjr ksf1xhflYbM2weI4ugAChqx+cijM/2X1xZVgVh7gDm9qiLvMGmyUVLfxdIrZZAoZ N/vWfG104qrBT5vuiYYKgCYVwoS9eY/y2ng3gYAYEvNlGT51dQWTS5hPRSQ1xMSh L6Dv/vm/AJoCK5ttefQ3+GKqJmaFJ7LVBa7BMbtQdtCzoIwnd8vvaajSGi8k7B/2 d7a7bGvjVixflzz0bfgMKdee8GqT2WdUjIxHq3nANE8hs4dCfek3z3+cjFCh/WpB YxFWrH0oXg== =zUbA -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIZAFgACgkQmmx57+YA GNm4vw/+MGF9aJlAxZcghNsQJ7oUQ6yTYGPeXqLEKF+03oJlk6xrJV+5DFH3UUj5 fmE1x/PdSX1WzyjMBrw5zjyuW2zoT2TWEU6mLeYI7F5FNWDI0+u5k2rqKe/J0WE3 g8grTXqMiriHVjRtgRGjrzKRHzw8UPFlCtuT3CV6Bfx+20sUg9l1qr/jULavPTeS tYIdVjp1H7wu6TG1rGze1cC3EtaOV4DGoVbE7vLa7pG/MCHE9z+4Y4TuC7Hx/877 JuypfpJWm12J92bpinIZjshTLDl0ei1n/mv2J+t7R8plTY2DuKJOeFvfNL6ubZ2A a/oBgXQ42XeK/hnUPcvrweKwjFPG2UQLJC96w+INnrKqopWxPULTOHhMkj2grqjK q5Hl7EfLja4R5fXS9+//lZisTyaAQKNacRGDZEQntuyNZKS9aZhFJqUsvt5dyZF1 s8CLjEgs63Bg5ehgwjEsJRx0jce6jqh2kcTp9/T1CN6lTUHWJ9sCto1oYEvs+nRi rM1r+Q1gtW3vphckcdtczOwxO4qxohK90sqZJBCULQUOJ6Y2Fj+0zLU5nHgJPzxK F7IyJ81wwg+JT2kBbM2QARAKxpymSR2da0nFqUvRkgBuT8C8TTVrTlQwljAkx4wg tnRYyDR05j61SIOZxj3NJ1HOe0ot3AB1OAojw/zULsQxjV/tLUw= =82Kp -----END PGP SIGNATURE----- Merge tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung clock controller changes for v5.18 Add support for Tesla FSD SoC clock controller within Samsung Exynos SoC clock controller drivers. The Tesla FSD's clock controller is similar to Samsung Exynos one, so entire driver structure can be re-used. * tag 'samsung-clk-fsd-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: fix missing Tesla FSD dependency on Exynos clk: samsung: fsd: Add cam_csi block clock information clk: samsung: fsd: Add cmu_mfc block clock information clk: samsung: fsd: Add cmu_imem block clock information clk: samsung: fsd: Add cmu_fsys1 clock information clk: samsung: fsd: Add cmu_fsys0 clock information clk: samsung: fsd: Add cmu_peric block clock information clk: samsung: fsd: Add initial clock support dt-bindings: clock: Document FSD CMU bindings dt-bindings: clock: Add bindings definitions for FSD CMU blocks Link: https://lore.kernel.org/r/20220204154112.133723-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Michael Walle
|
3c552889e4 |
mtd: spi-nor: renumber flags
As we have deleted some flag, lets renumber them so there are no holes. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-33-michael@walle.cc |
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Michael Walle
|
e9d663a2a0 |
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
Now that there is almost no special case code left in spi_nor_sr_ready(), the return check looks odd. Move the function call closer to the return code checking. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-32-michael@walle.cc |
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Michael Walle
|
e8fd3b4b26 |
mtd: spi-nor: spansion: rename vendor specific functions and defines
Drop the generic spi_nor prefix for all the spansion functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-31-michael@walle.cc |
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Michael Walle
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51c55506a7 |
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
Now that all functions using that flag are local to the spansion module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-30-michael@walle.cc |
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Michael Walle
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837d5181be |
mtd: spi-nor: move all spansion specifics into spansion.c
The clear status register flags is only available on spansion flashes. Move all the functions around that into the spanion module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-29-michael@walle.cc |
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Michael Walle
|
6235ff040c |
mtd: spi-nor: spansion: slightly rework control flow in late_init()
Don't return early when the flash is smaller than or equal to 16MiB. We need to be able to register hooks for all sizes of flashes. This also has the benefit that it increases the readability of the code because the action, i.e. registering the fixups, is connected to the condition, i.e. flashes larger than 16MiB. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-28-michael@walle.cc |
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Michael Walle
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2b18a18ea7 |
mtd: spi-nor: micron-st: rename vendor specific functions and defines
Drop the generic spi_nor prefix for all the micron-st functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-27-michael@walle.cc |
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Michael Walle
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8f938262a6 |
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
Now that all functions using that flag are local to the micron module, we can convert the flag to a manufacturer one. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-26-michael@walle.cc |
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Michael Walle
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c770abe52d |
mtd: spi-nor: move all micron-st specifics into micron-st.c
The flag status register is only available on micron flashes. Move all the functions around that into the micron module. This is almost a mechanical move except for the spi_nor_fsr_ready() which now also checks the normal status register. Previously, this was done in spi_nor_ready(). Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-25-michael@walle.cc |
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Michael Walle
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56b852e863 |
mtd: spi-nor: xilinx: correct the debug message
XRDSR is a combination of xilinx and the RDSR opcode, but the register is just the status register. Correct the debug message. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-24-michael@walle.cc |
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Michael Walle
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8b7a2e00d1 |
mtd: spi-nor: xilinx: rename vendor specific functions and defines
Drop the generic spi_nor prefix for all the xilinx functions. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-23-michael@walle.cc |
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Michael Walle
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8b4195cd6d |
mtd: spi-nor: move all xilinx specifics into xilinx.c
Mechanically move all the xilinx functions to its own module. Then register the new flash specific ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc |
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Michael Walle
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9fb4beb1b0 |
mtd: spi-nor: guard _page_size parameter in S3AN_INFO()
The _page_size marco parameter was missing parentheses around it. Add them. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-21-michael@walle.cc |
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Michael Walle
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66cf87c600 |
mtd: spi-nor: export more functions to be used in vendor modules
We will move vendor specific code into the vendor modules and thus we will have to export these functions so they can be called. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-20-michael@walle.cc |
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Michael Walle
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4cf1c7bdc5 |
mtd: spi-nor: allow a flash to define its own ready() function
Xilinx and Micron flashes have their own implementation of the spi_nor_ready() function. At the moment, the core will figure out which one to call according to some flags. Lay the foundation to make it possible that a flash can register its own ready() function. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-19-michael@walle.cc |
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Michael Walle
|
b44aa9ac6b |
mtd: spi-nor: slightly refactor the spi_nor_setup()
Instead of always using a function pointer (and initializing it to our default), just call the default function if the flash didn't set its own one. That will make the call flow easier to follow. Also mark the parameter as optional now. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-18-michael@walle.cc |
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Jagan Teki
|
80253168db |
drm: of: Lookup if child node has panel or bridge
Devices can also be child nodes when we also control that device
through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
drm_of_find_panel_or_bridge can lookup panel or bridge for a given
device has port and endpoint and it fails to lookup if the device
has a child nodes.
This patch add support to lookup for a child node of the given parent
that isn't either port or ports.
Example OF graph representation of DSI host, which has port but
not has ports and has child panel node.
dsi {
compatible = "allwinner,sun6i-a31-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
port {
dsi_in_tcon0: endpoint {
remote-endpoint = <tcon0_out_dsi>;
};
panel@0 {
reg = <0>;
};
};
Example OF graph representation of DSI host, which has ports but
not has port and has child panel node.
dsi {
compatible = "samsung,exynos5433-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_to_mic: endpoint {
remote-endpoint = <&mic_to_dsi>;
};
};
};
panel@0 {
reg = <0>;
};
};
Example OF graph representation of DSI host, which has neither a port
nor a ports but has child panel node.
dsi0 {
compatible = "ste,mcde-dsi";
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
reg = <0>;
};
};
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220202160414.16493-1-jagan@amarulasolutions.com
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Arnd Bergmann
|
877d1d8112 |
STM32 DT for v5.18, round 1
Highlights:
----------
-MCU:
-Fix W=1 warnings for timers (duplicate unit-address) for F4 and F7 series.
-Enable DMA2D on f469 disco.
- MPU:
-General:
- Add new board support: emSBS-Argon.
- Add dma configuration for all U(S)ART nodes and disable them in board files
when they are not needed in stm32mp15.
- Correct GIC PPI interrupts on stm32mp15 and stm32mp13.
- ST boards:
- Add EXTI support on stm32mp13
- Add DMA, MDMA and DMAmux support to stm32mp13 (iso feature than MP15)
- Update SDMMC1/2 support on stm32mp13: sleep config, update version to v2.2,
update the max frequency to 130 MHz.
- DH boards:
- Enable rproc to control the CM4 and IPCC mailbox to interact with it.
-----BEGIN PGP SIGNATURE-----
iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmIY7cYdHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIU+ARAAhKa66mPq5OyeaK5n
KC3JFupCSfMx9xIDaElFAEfmjYcju1ZEo9kXA8j7fIwjzcSmYzr7jFTPHu8Zd9Zb
SEjSS+5lLn/Lfps8xxI3sdhNRUob2MpOjptj2SYCTB4tXf9t0vc6+mB6Lr40RKXT
WS4wWCbVv8QZuDP5kQvvLaPNnPEA44BZhZ2DcqxunZvJejpBMMOMTx6FlKdovrBi
aWzKvN85Gjsa7gb4WUKxCPFTm2Ytl5+92squ/QAtDoKMT1AUcYGE4l9qgLNVhOHz
1pOY+JweeAHWcqUeYROh6x7KZ7mW7nSa4tIMsholOuebvn8OXinDZUgS7VaQtYDi
A/DGDwdhdSfuQal88BQeM4nSZ6Nixbd5ctFnN8SM+cBLV+x/ssgT/BP4x6xtcsGW
fBNdSmz7VvYQgY7e8ejDaXtokitZAtOFeWvssjZInjzfX6uo/uwGoXwQP2t7kYCZ
9S7jCRxDjilIJCh5medZHzfnXVRw5ywZKNb2qP6iKRYhLQ1KLsnDpPbMqujbCDWH
gFkws/YFvlKFnv5p/vp/dZFNCXSMGV+Pr30GSYSJCpUMlvKwhsuuywiQ26/rqGtP
DxfSK6p9cAq5Q4fl/xNN4q5IIs6UVrqhOr2flvK5qCUpeY1DzNrgFkun6sXqdAOl
wbajnzR1K0twmYaZTVFlTfJmQMM=
=VAh+
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/tsACgkQmmx57+YA
GNnZSA//UglEJDhn9uyyuQMEgwpxFla3O1/iRQMKU/rojii8HLs8rypsJMr46KnV
Zl+jTeIUDH/VZX1Oz6dmV16X4c038he0hf5gDRJzq+5cOF5I/E/e4klsBXA49zhK
45f00RdtRPwD4m7wh9wcQ9kEmT8vNjDcu0E4m4NVVw4zohpiWKUxNjlg+rUNbDyo
K5rAPEVJpsOWGo9mf8W3rVZgtRwNVPKDjAd85MbEQZrCVeFR5cdugA9nWzbhX38I
ypZy5315pm7cq8ooFKV8I8pC+0pGJH5T1l0gb6kFAhuYhzonXkMTDIY/2+ggptGJ
9reTcJHo89Lx45uPJxgPQyAveiH5G1bDeK3bMIOWkVmuHXwkm3F8Tf8nihoMMPan
R9xWbmVTnHFPLOOeb9G6X9Bd1nO9mr/7HWXNxMubW9VTfZYCwu3GLsuAPbclT92z
J/Gu+VjWsveBZoqTK9tJImhpMtBx6bhykORfZf94ImXN9Jfx+CNl774xQyROXzrL
DJXzLSHgg5elvBW6gXy9gBHJqdhfu6yHsNQS/wE20g+Op2hVWvXmgOUI6XrJvw1l
WuqPD9eCpMvLKGJ0N9gMsuRmAiNGwtNmLMTozWOXMrM0QZ11hJkuHG6HXctrnWOD
edapidUssxPsm0upq+8S1CiGXuaj4qq1TDOaj1tSmrX6p0hf11I=
=4fl1
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.18, round 1
Highlights:
----------
-MCU:
-Fix W=1 warnings for timers (duplicate unit-address) for F4 and F7 series.
-Enable DMA2D on f469 disco.
- MPU:
-General:
- Add new board support: emSBS-Argon.
- Add dma configuration for all U(S)ART nodes and disable them in board files
when they are not needed in stm32mp15.
- Correct GIC PPI interrupts on stm32mp15 and stm32mp13.
- ST boards:
- Add EXTI support on stm32mp13
- Add DMA, MDMA and DMAmux support to stm32mp13 (iso feature than MP15)
- Update SDMMC1/2 support on stm32mp13: sleep config, update version to v2.2,
update the max frequency to 130 MHz.
- DH boards:
- Enable rproc to control the CM4 and IPCC mailbox to interact with it.
* tag 'stm32-dt-for-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (43 commits)
ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13
ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f7 series
ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 series
ARM: dts: stm32: Enable EXTI on stm32mp13
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcor-avenger96
ARM: dts: stm32: keep uart4 behavior on stm32mp15xx-dhcom-som
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-picoitx
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-pdk2
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-drc02
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-odyssey
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-lxa-mc1
ARM: dts: stm32: keep uart nodes behavior on stm32mp157a-stinger96
ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0
ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0-of7
ARM: dts: stm32: keep uart4 behavior on stm32mp157a-iot-box
ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-edimm2.2
ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-ctouch2
ARM: dts: stm32: keep uart4 and uart7 behavior on stm32mp15xx-dkx
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-ed1
...
Link: https://lore.kernel.org/r/893924a9-bcc4-9fa9-4f8e-7f56e77f6854@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann
|
581a1f8c9a |
Compatible for the rk3568-usb2phy-grf.
-----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIX+X0QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgS0hB/48WJFJjU97Jk5Mc0nCoE+Phqjl7qllrNhT Hca1kDcSgYaSEYh3PjBL9rKiKzwOvBVLCL6qtt0Jn5ax4yu602ylva+lqA+F1FJ+ G1qTWJYa/oZ0k1wzQoCtejSqUNhEtjNmnH0M7/RETU6W1dC+1TxLS+RD4llLEvYa vg7I6lHe+JoR8K+RBr13cPYXtxz54WOcCdHJ5ZmKX4hBDfXwwln7RVDY4SKk6eQG e8lW5VDM4Lj2bI3DTnLMsqNGe3IdjicXCZ8isrIJe34B0RxCSu62/fruQ0hgdO8F b72meSYEvs5G6nlKM4SIFDmViY/lWR8CbBmoVOyYdnrsfk7zl2xO =EwLL -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/pkACgkQmmx57+YA GNnRKhAAn5ZH740lXdGruYmH9pZhshYWTqstTSeJJXCCjBSmlcTEHPksBjIfuj+2 ri/MQpFJUtNH1FXW3I5lLDMki8lVlLGRd94hbzo6vGOkctH0mI92Z/aFEpcCXhuw yh86PpbiBAYTdOJMSvhTFAxyoycRxkSvRpBcxize1oiMWpUo6GiP1K8GgQRaW9+f 2hkLyRmTAhtj+6FyE8iPkQFFbAPDFqUwi1xk176QpvVoI71wcItuzqONuBYmiEXK B+hfSFTfcjKw1Dhj8qMtosZts8LPF2Nz6BRdZAT/xZ8bFWisa64SbbChUNEsnQzq z0KLHO0zTC04ERrkY9+TU6RVG7x6la9O3MifCD/WAuGuAp/eq4pMqBFqvwps3Gz/ nHFkkaShSgh0IXXn8rvQt8mOQnmtvCKynFJSj/ot4aXgwHIwNVFP4yFaUY1p37FL oWVghEDrbkR3pjnNgEalaX37Bt/t+gbu5zR2CctrSWwBjJFrg2Vgyl+ARqNq3I1N 0xHnF3BAX9v8auf6xS+j2SSZ8p5R8yYr9uXiPHvI/aBGFzHQfzEvU7MsQpH4ZRAG 6F0V8xq0cyTsLHddpArZtI3Pq6RYR8dxBW884Ouje1Z7LbXgXsfWQWC3lmn2UoFK oX0FsEEijN42VLqj8hKlkMGpYjPhsLLTVFmUnduPIxahe4dF7mo= =ecoW -----END PGP SIGNATURE----- Merge tag 'v5.18-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Compatible for the rk3568-usb2phy-grf. * tag 'v5.18-rockchip-drivers-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: soc: rockchip: add rk3568-usb2phy-grf Link: https://lore.kernel.org/r/9977257.a15B8eIVjX@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
b610c55bdf |
Arm SCMI firmware interface updates for v5.18
Few main additions include: - Support for OPTEE based SCMI transport to enable using SCMI service provided by OPTEE on some platforms - Support for atomic SCMI transports which enables few SCMI transactions to be completed in atomic context. This involves other refactoring work associated with it. It also marks SMC and OPTEE as atomic transport as the commands are completed once the return. - Support for polling mode in SCMI VirtIO transport in order to support atomic operations - Support for atomic clock operations based on availability of atomic capability in the underlying SCMI transport Other changes involves some trace and log enhancements and miscellaneous bug fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmIVQcYACgkQAEG6vDF+ 4pgiLw/+NA01jx1VMNSUTCsSLvDQ0ZXCjEWEXaIR1KkdKELGu7wwItIqBSisXfmx 9/NBGBydz9q700NGevIjRDiBo6JThmDf/tTg21OdLvRY8Dwqfktz7JO4Jsne3cwW hz1UTxyStUTNqt4Omprf1xzlKKerSuzav4KB1MtpAyzoBV6RFHglaznPCXL7mkic 9+9WPeVcwQxQ5ZXuwV2WDrJ9S8IZzMzZh6woIM/O4fdbyXGv28NfVt1oRidOPJOE uMsxF/LcvUsQpQBOU9cTqkkmBCKRmzY7xT1JK58DcteSrleYoiZJqT7uFxI92i4Z DqKMMUcbJVzKErBYyBHCA62cfRBvOV+OLhh8dzR2c40a+Ecoy5vQHGAEgMUwZBWx 8ztRDlBFzWxNSCyn5fh4IuV1POygrH8UTq57s+Mwr+hrr93Gb2JoxH3UL3kgGTJX c9AFhLPNWDD+cwJouSD4y55kqik/53+vUqOrCHQkPjV4cz5Y3+P0uIraesh7NHo9 Mhnoudt7IZdJVowvEZyjQ4kp38t0G/M13BK/3Tw9EtlcFXoxOSP0AfLc1Il8nbRT afKWVBfTZbxpTWnLsf5SkHXJgyO1tCEd51wZLqejWZqqwrhbNoqA+HyxdtIIvi1o n5bS7qQ2wiuu3DsnJlYrJXTj2YlpUGm1MBHgmFUHtMUj55XpmEA= =jIoO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/ksACgkQmmx57+YA GNkNRw//YzZGhm0MtpPCe1jNv2bDWVq75v8bzDL217n9QJw1dpx0ru/xkDJDhmDP t7vfSFFPfE2o/jXzMOuO8c6E1/b0cdxd9z8V1SPIHSwPXA/ZM4OdMKZJdwK6OK6T HCW1PJJi+5ktu0mWbeflCW/isIQv0Y485yNH4q8gLSWisufevm+1LktErhNarQst lG7CR9KclOZzqhVfT49vXhly/HSWVjUvYJfAPPERIQDwDvKSWjkx05ZPuc8l1DJU 8Z2164E04uTwU1p0154pmay9eY6xcBpTXhBkwFxwCfjKu0Yc2ViVRuGJh27x5TXB ScAF7iRhjC2sk4v7H7UEFjVVAQix8aNyeueXcB1+6adSkCnerO/f4yT5uylbm7e0 Qj9XrqV1cF6GwE1ukRGa0hCySGH9xEz3No6ueEqCQQgbvVJ4o7RoUBoapnZUfx8J ee/C4EHd/7uxBm0ygQ07F1+RbLeWw6aLSVeM03bY+bz9LKkPxELrgP98WLvvGtzy Xj6k98DMdmZsCwcp3Z4va9gjopjgM4Z7pWnABihXEkidZXGodMMAQCAUU5gmZeKz FSubYgjrGojOy00XOQsggw+CmNHLGNvQoFLjaRtRxHLJYewyjuE7zCcSOdqTsjI4 BKEUgtakDEEFoSA27ycjne23VyhxI3mF3yC8LBiAkzbksuMQXvA= =qTGM -----END PGP SIGNATURE----- Merge tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers Arm SCMI firmware interface updates for v5.18 Few main additions include: - Support for OPTEE based SCMI transport to enable using SCMI service provided by OPTEE on some platforms - Support for atomic SCMI transports which enables few SCMI transactions to be completed in atomic context. This involves other refactoring work associated with it. It also marks SMC and OPTEE as atomic transport as the commands are completed once the return. - Support for polling mode in SCMI VirtIO transport in order to support atomic operations - Support for atomic clock operations based on availability of atomic capability in the underlying SCMI transport Other changes involves some trace and log enhancements and miscellaneous bug fixes. * tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (28 commits) clk: scmi: Support atomic clock enable/disable API firmware: arm_scmi: Add support for clock_enable_latency firmware: arm_scmi: Add atomic support to clock protocol firmware: arm_scmi: Support optional system wide atomic-threshold-us dt-bindings: firmware: arm,scmi: Add atomic-threshold-us optional property firmware: arm_scmi: Add atomic mode support to virtio transport firmware: arm_scmi: Review virtio free_list handling firmware: arm_scmi: Add a virtio channel refcount firmware: arm_scmi: Disable ftrace for Clang Thumb2 builds firmware: arm_scmi: Add new parameter to mark_txdone firmware: arm_scmi: Add atomic mode support to smc transport firmware: arm_scmi: Add support for atomic transports firmware: arm_scmi: Make optee support sync_cmds_completed_on_ret firmware: arm_scmi: Make smc support sync_cmds_completed_on_ret firmware: arm_scmi: Add sync_cmds_completed_on_ret transport flag firmware: arm_scmi: Make smc transport use common completions firmware: arm_scmi: Add configurable polling mode for transports firmware: arm_scmi: Use new trace event scmi_xfer_response_wait include: trace: Add new scmi_xfer_response_wait event firmware: arm_scmi: Refactor message response path ... Link: https://lore.kernel.org/r/20220222201742.3338589-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
c8812c2a08 |
i.MX drivers update for 5.18:
- Drop LS1021A device check from soc-imx driver as it's unneeded since commit commit |
||
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Arnd Bergmann
|
25b67f373b |
TEE shared memory cleanup for v5.18
- The TEE shared memory pool based on two pools is replaced with a single
somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
easier to use and maintain. The TEE subsystem and the TEE drivers are
updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
functions above.
- The TEE_SHM-flags are refactored to better match their usage
-----BEGIN PGP SIGNATURE-----
iQJOBAABCgA4FiEEFV+gSSXZJY9ZyuB5LinzTIcAHJcFAmIP5coaHGplbnMud2lr
bGFuZGVyQGxpbmFyby5vcmcACgkQLinzTIcAHJdLQg/9F+9wtUsM3sJAitaB0DN1
tTd8Iwt0Ir8khuac56/pMcVlFF1dwBAFy5vnAKKSGF0nzToyEhOc4uRsOA0vvQ4s
EtTX7ONuHjPR18faxJbtLHPl3tSjGxkwtrBo5IvCapxaYsJK8x2XEamr9ih7r5nZ
KwSTNgiGZ+WM+IgwgZIFfOoB4pXnkQZAf2UBAdK2W1dVpIOoJzLpiS28DNgA08C5
sUduKi2GvmaieTqu6QHY2FJNRAVgYrzuyXIgfQ+Kjsa/GDMZ6CS9DB3BBt1D4xyM
OzIl4/Y2nZqJ6EFhuFtWIQIuMLlw0HiM08d/PC4vW05EwKmeJ5zTs+I9nJQEnPKN
n4SfwqKIIq5KeYeT0ByVuGwm/JET4YXvL3d9EqkDtFAwnkT0Jx7o5GgFQbj1+0Z9
RvmWWy7VFPRhvLGsPpkuJnGc9rD4XVtzFw92K1VRmarQnjQFmD2y7DvNEEXokLCv
Z4GV3bz7ntmURJsOoMpt56i9WboXkjFmsaIqg09ShPRC9EB+9RMvRNEwE72FZmlH
RIMl5Vx4SkYbY1FlaiJ9BSctcdQD9HES17D5z5l6Im3JjMbFeKvLLQCJ/Ch3vxNj
OujRhXsEO2g9uUXwh0OveK8mEh3bz+GE/uj+c7xZXb95ImswyK9fo9uLvG+Z6JVk
n9+xgsKUZlHwHkoofuXor4k=
=xOBv
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/jcACgkQmmx57+YA
GNk94w//VHkLJADLSqwh8AZXUwpBN3nCKtsEay7HbRmC9Nh4Zm/TQyYx79QmRnnK
kDxLVAFTapFLxQVo441jPfnjp2cSW0Oomhv3zLIPNE44Gb0jF+hqfbN3sLJLk5hZ
EiiRxnMEJ6KCbvLEXaSUqRfGoYkU98HF6vNzN0nme6Zq9f11GO7RsUGL1nLNrU7R
mGj4O1hr6QVWMCY5vvEYLkGZFj54jVb64UVYzmyw8Nt5IIbY2upCQFoeQYHtiIle
h354Wn3PgE+txzSKGGH0dw9hq2JPNFSwmx3psvw+9HUjYXGC8rfaJeRNTEC9oIaC
ALXqNnnu/kkhKt6rfkVaVuJFjefn/WjTCfEFyCRblwmNdi+DZfkcCkDh0Tj/4F6X
/hoLYC4XXt+bxvdi8I6+xH8ho+Zwsh3F9WXWAU+p1fR5/kOTpvYe10k+59lK+AUK
bbPCN2WQ+IB66Mt8OXAVRycXKrbGU32QTioWF7Jv5/ZgF1aTeAnzyoRnT9OI8FMz
sxqSNd/Lasc8czP+xdTrfisOy+7vRfSOPDgZ4BUVQLAZIDmuqiJo3Rtu4J72aZx2
Pyk680b3iGKORBGVFznF8DOWxNdbUbuQFxUzIGGKHtsy9++fyZzrwtjASmT9Bzef
ec6FVInEKt+f6nuMUZrMWRaWIZw3KGqWRnkX47k86PsCAh3HDvo=
=0vIF
-----END PGP SIGNATURE-----
Merge tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers
TEE shared memory cleanup for v5.18
- The TEE shared memory pool based on two pools is replaced with a single
somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
easier to use and maintain. The TEE subsystem and the TEE drivers are
updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
functions above.
- The TEE_SHM-flags are refactored to better match their usage
* tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
tee: refactor TEE_SHM_* flags
tee: replace tee_shm_register()
KEYS: trusted: tee: use tee_shm_register_kernel_buf()
tee: add tee_shm_register_{user,kernel}_buf()
optee: add optee_pool_op_free_helper()
tee: replace tee_shm_alloc()
tee: simplify shm pool handling
tee: add tee_shm_alloc_user_buf()
tee: remove unused tee_shm_pool_alloc_res_mem()
hwrng: optee-rng: use tee_shm_alloc_kernel_buf()
optee: use driver internal tee_context for some rpc
Link: https://lore.kernel.org/r/20220218184802.GA968155@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Arnd Bergmann
|
bc5ede20b8 |
Small simplification in AMDTE driver
-----BEGIN PGP SIGNATURE----- iQJOBAABCgA4FiEEFV+gSSXZJY9ZyuB5LinzTIcAHJcFAmIP2hEaHGplbnMud2lr bGFuZGVyQGxpbmFyby5vcmcACgkQLinzTIcAHJccThAAqhw9KVTDqrUxMz995VqB kJTqTpdvXbveayv6Ja01qC8diXJI8XIDPJteQLf5nflyk5YziOoFG1Xn24EM6CrT tsRdY9Z0/5wguhZsTYvDtpVtwm6cpFEgFRiyoW6UhHXvZ+ve8XSRwA6DQc1Iywz/ HrSIo3ni74O9lTZ0LGWp/2p1ArE7l3WqCknIC7hk8KCEJTzyBusaI7OWgi2ymHax 3Q64OZKCcKhIvGm7LDRd545t9yKLmCGL/l2JNW8x3Ulj68ibWyWJ7ASpQw2mJX9U Cf3nkuuq6KU1a1D8sq16nurSlmC1jL9qrXCRFX4hcye6JZcGav62zZswhT7fKvVK jfieMGelGA1pzjA4+ZwgXFK610AhrjLH+CV5Frh1art75qqb80CrY9cZqucrG9se sReN7x3gxBy+PPj6AUVP3oMnGkPpOl09zRoejvG107i3ccUGka9gVO8whAsBHWBV jgmOxLHufq4hF8iBBUK71+M+csHYq0tkfYCd26X3Cph3lS6ovTnDHIgCDE3ChATI 7Y7gKgIFGs/XUtZR3B6+uneU6kiQRmjKeyX7tbnfz+jgULh1BuOMYS3CDdB7AY2p GCjHReSmbgCl8Id8KSHWlbxATi0GWQu7aIVTzJJS1ktKqUIC0yzy1te/ShNrpgCO NahbcYVpPFfcUsScpi4llj4= =yDlf -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/i0ACgkQmmx57+YA GNnXMw/6AmrrQ3v2KvNdrmb/OEWg2skySRHLmgjpZliHPmSgbCFAV/PRVgjqRnAK rtQfIppCPTwdF+p+PXUKTgZJYMVzi+9BzYZuoR3JLzN9KE4uTO/7sTMmeYH5SmUM kXoUiSj4xFiLdqtI671tWLAiGHLAQl7wXBx6VBta3va3xyzpuAowp97RPWyA7x7H KopXYVQbwNAF2HkCS3KQVbFapTJ1p0W+tV7rqQv5H0vku15JVpixu43RmZM1Ks3s fUR9xxl4aOf7Qm6Ldv+7ETZ/XVth6dW221vFTuZ9cbQfiWOQGtw/Ve79DO+CSYpZ DmOUnI2IJM+xteq14EKIkk9oBSDgm3cAedZ3BLM52GqPTXYqR7QuJiVkbJrQSQ70 dcoP7FPfNeXugkyen86gKwO3ttrfa1o2zp1JR1KmG4tvZ5M1sYT3/2qIGNPSi7v9 PJGJcTfvB5cFM9K3CaW7pw5gz13r+kdTaObiLj3IDrgdwWupsbTzOsx4ppm4+ypz bfojYFfWLJwLZa4okvmyELeKcmtow+brRhZ7rBw7DbAYZolFfEofwvemZBWt4qJo ++VIgkAVCu4Y/vD3D9Q0oouab68RQUvekW1bYOF1lCtCNFFdo8ULAr0UF+MMegsY hi4NUBh5naU/TXZ50Jef5YqLAgpaQGX9I5JbwfRIAI67M9eFjlU= =zlRE -----END PGP SIGNATURE----- Merge tag 'amdtee-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers Small simplification in AMDTE driver * tag 'amdtee-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee: tee: amdtee: Make use of the helper macro LIST_HEAD() Link: https://lore.kernel.org/r/20220218175632.GA926082@jade Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
f289f1d8a4 |
Renesas driver updates for v5.18 (take two)
- RZ/G2L and RZ/V2L need PM and PM_GENERIC_DOMAINS,
- Introduce ARCH_RZG2L family for RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L
SoCs.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhiptAAKCRCKwlD9ZEnx
cG04APsGHw3HAPWLOABfiBWUNjwqRn2bNtyn1zqVGgjBR/mKJAD9F7ZMDq11f7z3
felk/bHWKSpgEDQpyaLy4po/QeXNygQ=
=9blS
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/iIACgkQmmx57+YA
GNncvBAAhQ3r7+ty5Iu0jFnLkKYTzDgas/WSf8Okn6QJ7SBdp1PDVkpabokGa3zj
A3u2pDQuVrLPh5P1Nav3j1p9rMXY/c1yLxTJqthEATA/FPGmszuOQMO+mV+kYAO/
FFko/PsKYRBP6Z7yiA4sy1umAYseRHq29cPvTjmJgXKyPd8UgsMex7RRSpH27myx
s4gkFMBo6Awi34bqEPs2H+XTsm2/R6EQrjjY3tvMZHfmU7Blars4EXlU/w+Ny6SS
lNw0rY77QvYh4O7YJgmI5DyeaFp62rsAuflb8Vl/Y7omrNZMbHQH1ffm9/DYfAr+
DyZ44xNZHdoxRathWoSZIQHHi2ikMCc4EeXZTYuuLZp+QKV1ofews8O8V8sAiw6/
HtWVsIfEydd6hUOId4mk4qIbk+R3OdwdhV1eJd7OYKtt48mQQkoJTJrVlF4+h34k
phnbXN2UHqGKYQ8I3pR6kkpgZSXmSrgpeFlr6Hj+xWByWprOu3blIFfxa2XVqgBA
9o8i6rWfP+/knfKnWMl1OqaGPXeKwpJyTibmoFlNrd3gQyVXoGzEAwtJuWdrz/l5
gF+HHA+DseMRCPYQrSZNE/tIYsf2fgxtaC+xGcaJHaz3WGdT5dug5veIJAxX2Hjo
acYnI9yPGWuJYKJP62eY34iq0DvCUKc8HA0WHovUXWck10Npixw=
=DpYA
-----END PGP SIGNATURE-----
Merge tag 'renesas-drivers-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.18 (take two)
- RZ/G2L and RZ/V2L need PM and PM_GENERIC_DOMAINS,
- Introduce ARCH_RZG2L family for RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/V2L
SoCs.
* tag 'renesas-drivers-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Kconfig: Introduce ARCH_RZG2L config option
soc: renesas: Kconfig: Explicitly select PM and PM_GENERIC_DOMAINS configs
Link: https://lore.kernel.org/r/cover.1645784470.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
|
Arnd Bergmann
|
15cc8d030c |
Renesas driver updates for v5.18
- Initial support for the new RZ/V2L SoC, - RZ/G2L product revision support. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYgZkdgAKCRCKwlD9ZEnx cATlAQC3oVCC+xvW+DYQagLO9ADPd8MNe889+p8Kw77xtGi2aQD9Ev9M0QgSzpBY /pXngnUMmHnAWfzzqRKZAUKWW4K17Ao= =85Jz -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/gkACgkQmmx57+YA GNkB6xAAv08XmMxg7bnN0H5cQp2tkn3LNlyWEVSZuu/x+XNc1RRG8oNnZZiS9Voe ZTh5EsFxoseeHkNIQxS+WVxrd2jN30Tz7gGTp2/xnbxas+aVomDzo+H4qtgSWK3N P0P1PSXHxwUApszPCPuyyXqNoxUmJjn+6OqqPkxpkqwspQYXc7HgWuB5Syk3JUF4 ZvOTCCgnKKaFJ2Dp5VzwnSYJd2eeHCV6lk96BkO1WsUdEfYO9dm+e/Ig/utU3yhm 3QDGGrRADYoKx+TM/c+oNJoNcQ4R7JbzzUtY48MQEvx0IDE0e5Q4ocAbf1N7YjRs zFR4+E2c/4L5vnUcY4mig/8MWL1tvEVrVqJIAquIzUU04JOr+hjQxw124raJMWdA yX58/gv1UoCAcBr2vLln5gX0gILpJCM+obh1ft4f1/Zlqwuv+6CFpNdpWWGgwSFU V4GX1WHUE7EJ2PW0t6292vcHZmHrVZBTzEzNh5v0kT6A5jPsV5/fE1Si/uWPnegF CTWuunghFczDGLQ6LXEfGg3omN+7MNl7g3xFxWxyYEHh5ED9qQYbp4w/ivJk5mG/ hClbef+EOyi96yDIxeC1Oy579SPLrV59YLbz0yrqiMN2ADPOxumJPOSHBmqWe7TL Jad92hd1bUfejeqoQKQHprPVC2arcitukCXiqIDr/QbyLG4no50= =OgHF -----END PGP SIGNATURE----- Merge tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.18 - Initial support for the new RZ/V2L SoC, - RZ/G2L product revision support. * tag 'renesas-drivers-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add support for reading product revision for RZ/G2L family soc: renesas: Identify RZ/V2L SoC Link: https://lore.kernel.org/r/cover.1644587208.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Rob Clark
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9e4dde28e9 |
drm/msm: Avoid dirtyfb stalls on video mode displays (v2)
Someone on IRC once asked an innocent enough sounding question: Why with xf86-video-modesetting is es2gears limited at 120fps. So I broke out the perfetto tracing mesa MR and took a look. It turns out the problem was drm_atomic_helper_dirtyfb(), which would end up waiting for vblank.. es2gears would rapidly push two frames to Xorg, which would blit them to screen and in idle hook (I assume) call the DIRTYFB ioctl. Which in turn would do an atomic update to flush the dirty rects, which would stall until the next vblank. And then the whole process would repeat. But this is a bit silly, we only need dirtyfb for command mode DSI panels. So track in plane state whether dirtyfb is required, and track in the fb how many attached planes require dirtyfb so that we can skip it when not required. (Note, mdp4 does not actually have cmd mode support.) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220223191118.881321-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org> |
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Alan Stern
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f6a9a2d64d |
USB: core: Update kerneldoc for usb_get_dev() and usb_get_intf()
The kerneldoc for usb_get_dev() and usb_get_intf() says that drivers should always refcount the references they hold for the usb_device or usb_interface structure, respectively. But this is an overstatement: In many cases drivers do not access these references after they have been unbound, and in such cases refcounting is unnecessary. This patch updates the kerneldoc for the two routines, explaining when a driver does not need to increment and decrement the refcount. This should help dispel misconceptions which might otherwise afflict programmers new to the USB subsystem. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Link: https://lore.kernel.org/r/Yhjp4Rp9Alipmwtq@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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Arnd Bergmann
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c253bf70c6 |
NXP/FSL SoC driver fixes for v5.17
- Add missing SoC compatible in existing binding
- Replace kernel.h with the necessary inclusions
- MAINTAINERS file fixes
- Fix memory allocation failure check in guts driver
- Various cleanups and minor fixes
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEhb3UXAyxp6UQ0v6khtxQDvusFVQFAmIQNLkACgkQhtxQDvus
FVQEhQ//d2cWdVvGUL5hqz+bEdu5b9XmiyLYlN5u9ur0j6D1q8GGuNThC68N0y9E
mmZfKS2WJHWOodowXEtcMaa27Zra5NEHZZoXS6i11xKnX6vnwB+bjBVGZSk3yJr1
YoRWRi8p6jnZ1RY2ImBk6WnPS/6yIJ8NrtpNFaASnllXA7Le9xAiucXv3aNRaYgm
qlvxv3+FEXQkKxC6jo/XnUjO59jpsV2GzS+KkUDDMvSQuWr5W+yxT+82KquK40eP
mwfvzH4qiJNxRTjFEZufSeBPJF8IU3ojwcV5QOI1syO4OpC6ZLCaC9M96TNwIRLs
zcAfQ+iY8+pcSLoTeGkvdi/LE32jf+/V0oPFrAHd0YaOSKA+Bc2zuznW500MQrwj
cCF0VySacP74mRDv1ddgQEAJTSVK+/uwvOjX46AVidNAchl3GCYMQhEFlwwHEGee
R6QUpipHvGOKMsIkwSrHP4tHcvGsPR4+UivLtkBQjOMqTbNEoUDtdOTYY5AYhsqU
r6dGQ5cLDuYYbxKzi7E4Gw0IPESaYgohy316sNPHoBqNYE32OtTO06oG30hVLWvE
5k0Cj5XqTWBgwnGeMvCb3FJmOmM1PVPS2Tu1bKYcUNuR9DthMmcrPwpqe3Jz/jEN
Uv6afsdvCE0oOO85nCg2KpgQy9sziGbXDqF6OJy6eeXbou7aSPw=
=RAoa
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY+J4ACgkQmmx57+YA
GNnrVw/+M8MYpJV65PjBrCgY5548Zd60zvhwm02eC0QwGFuteg3wgO+EyC/nPBXF
dSHKSBcPM6Dt4bqnJQVRlHmkfF10lT+JD+2gGikh6Fc6EXDj0TegQnnnorXRJT4J
7uy52KEdc1GsDU6hwDIbGr7Q7Ih/syTOKT3kj5j3OoSYjEjaRgwbYqOfAwT7j0St
NrhJPUKwtnn72a/6q9L9jKrakT6dSUw42HKPiyaoQAG/7EzsFRUl8pkqybgGKTPV
UKyOB2UH1B3c8/9sLA19xkCAl4A3DXh4odcr7LRpfmhBH2/NBO72WhqeAGS5uBnJ
FHBEIamztUndfhU317OITf25MMNHCBWz3lGxY8FH8NlUxd2LyQ6nR1h7iGZLhAXE
rHxamYVGaBoep7E3Vy/D7qJACyG1tv7L3o/btCi2r4444Fhdk+gvKTbDdPcy/dHn
jLqYDgVinoejW1KqRBt8ixPM6Yqp/v8AS2ACmt+SmoWoKaNzMyL2NYoQNPzlJ8SZ
ZT3zLw4H1SIAvu5qOFz0qRYU2vuDNdBL+moAV9a/MU67fvcmyXZHsEGjMwYmW/H6
S4nWlqSmYLldAmu1wff/+oqZw/1VTdy7ryzN56ei7TtEmvQ+ov15FZuc23ZIBmK1
EECagK8LdhZiluYzU0oYjXkkrcjn9YCPbPgflKQK1EoJvBI6BfY=
=gn5p
-----END PGP SIGNATURE-----
Merge tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/fixes
NXP/FSL SoC driver fixes for v5.17
- Add missing SoC compatible in existing binding
- Replace kernel.h with the necessary inclusions
- MAINTAINERS file fixes
- Fix memory allocation failure check in guts driver
- Various cleanups and minor fixes
* tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: qe: Check of ioremap return value
soc: fsl: qe: fix typo in a comment
soc: fsl: guts: Add a missing memory allocation failure check
soc: fsl: guts: Revert commit
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David Gow
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5debe5bfa0 |
list: test: Add a test for list_entry_is_head()
The list_entry_is_head() macro was added[1] after the list KUnit tests, so wasn't tested. Add a new KUnit test to complete the set. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e130816164e244b692921de49771eeb28205152d Signed-off-by: David Gow <davidgow@google.com> Acked-by: Daniel Latypov <dlatypov@google.com> Acked-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> |
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David Gow
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37dc573c0a |
list: test: Add a test for list_is_head()
list_is_head() was added recently[1], and didn't have a KUnit test. The implementation is trivial, so it's not a particularly exciting test, but it'd be nice to get back to full coverage of the list functions. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/include/linux/list.h?id=0425473037db40d9e322631f2d4dc6ef51f97e88 Signed-off-by: David Gow <davidgow@google.com> Acked-by: Daniel Latypov <dlatypov@google.com> Acked-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> |
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David Gow
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d7fd696c12 |
list: test: Add test for list_del_init_careful()
The list_del_init_careful() function was added[1] after the list KUnit test. Add a very basic test to cover it. Note that this test only covers the single-threaded behaviour (which matches list_del_init()), as is already the case with the test for list_empty_careful(). [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c6fe44d96fc1536af5b11cd859686453d1b7bfd1 Signed-off-by: David Gow <davidgow@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org> |
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Uwe Kleine-König
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4036b29a14 |
ARM: mmp: Fix failure to remove sram device
Make sure in .probe() to set driver data before the function is left to make it possible in .remove() to undo the actions done. This fixes a potential memory leak and stops returning an error code in .remove() that is ignored by the driver core anyhow. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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022e5220f2 |
AT91 & POLARFIRE SoC #1 for 5.18:
- sama7g5: CPU idle support with CPUFreq operating points defined in DT - polarfire: addition of the soc system controller -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYhjItwAKCRAfOrpwrNPN DDLmAP9CKK9j0y3YEs69vXYO4URTc5FrpRdZ976mHZdvl5ZJpQD/SK8k/AZhVwsV OUMN8zosXY0TiCRjsaLPq6MK9Nv09QA= =alh4 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9zUACgkQmmx57+YA GNltxA/+KgPQWmNQ3sPfkGq+rbCMof3misxS41OL64VUyT7VFau9nZeyJ7m8Vc4X CudkmTO39IgYLOcy6l51Pq8zeZ8jcMEQPntFo6fQUimo5slZQBNVuHnnCiWjpUdh eOQe5KwQb9fHPW/vMN0zKafckkVQXELo88ol54SorHqDwK/LU/s8iYYsUXByMJoa mxrZvg8/pXmQ+yyo1lpID0VfN+nWmOq4LVwSniF7z88M+J/H6R/A+KLqOoEyKvUN 1wawBdKHqmH/BftMnGP6oqFVFeOgH4BhMLPMSLp09rO5isx6vgPhWXvGh0PfL/+9 hUaOE+Hr7j33Yuxow97opx/Q0z+pqT0nyENq7/3cZpzB8V+WVJNFQeZ4Pm2A5jis NLRhm+V9gnRd8usZeepa8uvywo1aZHE2T14VcFffSPqgkOONyDj0V7DEP3gfZicA ezYIbUFHqU2hVsEmnxzXNDrvdUmI3yv77mK+1QXE3HBdd8DLDzpNOdzXED1ENf9p j2vBUX4XCiQVxSBbhA8ILKEh+xCUHDh6ZUMnMzQwy4hxa2RPfFPscr+m/YURDb8A EIfvG0qtBIe/CsVrD8XfhBTyewhFQKWxYUSDz0nl9OWhr3+Q/6yxJSSvAQoD40tS rYuS6JFDIJdB+wjt2Q6adR4xpCnEkfDL8ysWiYPMnTQ/mnmu2hg= =VBoe -----END PGP SIGNATURE----- Merge tag 'at91-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 & POLARFIRE SoC #1 for 5.18: - sama7g5: CPU idle support with CPUFreq operating points defined in DT - polarfire: addition of the soc system controller * tag 'at91-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: soc: add microchip polarfire soc system controller ARM: at91: Kconfig: select PM_OPP ARM: at91: PM: add cpu idle support for sama7g5 ARM: at91: ddr: fix typo to align with datasheet naming ARM: at91: ddr: align macro definitions ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency Link: https://lore.kernel.org/r/20220225121943.71494-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Daniel Palmer
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16018c0d27 |
ARM: mstar: Select ARM_ERRATA_814220
All of the SoCs that are supported so far are Cortex A7 r0p5. So it seems like this errata is present. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com> Link: https://lore.kernel.org/r/20220223064807.261878-1-daniel@0x0f.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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183fc8344d |
i.MX SoC update for 5.18:
- Add initial support for i.MXRT10xx family which features NXP's implementation of the Arm Cortex-M7 core and in some case the Arm Cortex-M4 core too. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUVkYUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM7IMwf/ch9nwSrW6lLdypPqQzs80fd7JVtx kZFeHrjxePtP2fhcPhT9PcJW5nBDmGkoxpuwbfTFjvm/UxMcBVIYfShk6Rposrcv hhnnCA3gx1bdnGVYTTv3d/5fAXVUoIbE8UsWLM1eOrJ7KNbevpC5353cuQNytTSp +P+wt2hHweuTDmvPRmDY6QJndM6rBwKqZ5a7Rd5pqRzGs7mMwr5cMvWMjecM50Ni FOQYt3YmLClQXyHBBhHBog72JVkNw65NR80o/bhdDIAXwXFqReABnToWFmoS+jwd jWif4Ibhq7DNNfxt+HRMT6mwHOViDl6VxzPZ0TvGnULb1YohMuwPmeM7cw== =kPTp -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9vAACgkQmmx57+YA GNnwshAAlfT3kDGwTXSKhwDtoFB+4hD6iiQfM0bO9sRoNES/LoyJEMD/RrZmB1Yv ZdZr3ghDPrNUHqOzhDNLnKznE+cVOPQgcE8LgoQxOspHpSN7YvCsh2nsgzWQyzQG LkRCdHEbqiVpmGSaNPsicvVfHTIAqwBkO+ToJw1mJ/6o1Fz31Ll4Qjy3LqbcIsNW 84T2TkWZRTAGY9XKKMTJkvCZ5IVhsNtlJNM+1lMs+UvoERORpOPcYoTSjQW3ALX9 OtgOBM0u6NOeuaUX0l5MZDNurHze0D7l8QMeUSeRUnQF8KCXxnV2tS1hAh2JMD1k 8N0xmd0KB0+/OBEGF4AXTHj8anL7gQMUZxEM/geMHezlfSU8gJJ21tweRUFJRKD4 EcUCsIOrEjnhdztOznYNzpz4NrsgoZuRkRfTOpnbn+inhRmhFbp0g55wsdjtAFUg TYzDN6amrj6FdjHHJDQ0X6NGkkpM5Wu2bS3RrZuiuaKerw2Ulyyv3bOJ/9Dv+H0t V+yLECGAMW9qeYw2cD3ZxiRjD+3dqV7BrpUMLljKUcApVf0uGoRaHALxHwT70HSu h3GpINmM751dcxPbNi6BJFi6TH7v+58ulsF+nZERyE+NA5UIUip0pnDeQlOQzJTZ lt+1Cjz6zSe3OduKrbRgc61CfcAUWU7Lpwep0RC3gM3XofktWFU= =tki8 -----END PGP SIGNATURE----- Merge tag 'imx-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc i.MX SoC update for 5.18: - Add initial support for i.MXRT10xx family which features NXP's implementation of the Arm Cortex-M7 core and in some case the Arm Cortex-M4 core too. * tag 'imx-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: Add initial support for i.MXRT10xx family Link: https://lore.kernel.org/r/20220222075226.160187-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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543f7961c2 |
This cleans out the remaining board files from IXP4xx and
makes it an exclusive device tree subarchitecture without any special weirdness in arch/arm/mach-ixp4xx. The biggest noticeable change is the removal of the old PCI driver and along with that the removal of the special DMA coherency code and defines and the DMA bouncing. I tried to convert the IXP4xx to multiplatform on top of this but it didn't work because IXP4xx wants to be big endian and multiplatform config creates a problem like this: ../arch/arm/kernel/head.S: Assembler messages: ../arch/arm/kernel/head.S:94: Error: selected processor does not support `setend be' in ARM mode I think this is because MULTI_V5 turns on CPUs that cannot do big endian, and IXP4xx turn on big endian. (It crashes if I try to boot in little endian mode, sorry. It really wants to run big endian.) But before fixing multiplatform we can fix all of this! The networking patches are dependencies so I am requesting ACKs from the network maintainers on these. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmIH7KsACgkQQRCzN7AZ XXNGDQ//dfQIiKC0uE4UEbKeDG18c1NpSDHomQQ/xGjnl9nenmOzsqg9pu+hrD+y eHNp55PmL8WKjXYV8wrbQd65BsnMGpiIh4CoT17BOM0vjQ7+l0KM9FqCuYTIXkyE +AR8ZbOYZDSNZA6bKCy8dT1tYZakx2IK02YEphiAU2hPsvWYTE2VTDSYzskbW7pu +aaCzPOnteQZM4cRMPDOmhq9FedaCnluom9ldTei0nEkFuDi0v947zUVs8M3o7gi rsZBRxfXlY86G3b8WdqL0jCcrsWsnLnP6TehSH7r/TbsFlzdv+GQpfZ8craDpTTW X5zhUQYreAYNY88Vy1UoVSci6BSJF/c8Q75lcLOcIuf/XX6ufyTO1YHDXxxSm04P 1cjunZzJs/YGx2dDgVfzSIXTBCMKovZcUVI5FfEP36wW3RA1WSa4cdWnI9alwlp4 yX7AtOtbxIZ2jiNQMV4qx9Yz8SzlVWF7E63S16XAiFWr8BQex1Lmh2u5BZLE03XW k9yl+dhqmTf+MlHS7y70KdwxY0XvJNZiHoCEIA2A0B7ayvl9ThkXOWOkYBZLb0hq SmlIHJkRyFLNxtVTvadq3S8fa1haS9qTONwfS7KCkCPp8XpE4QCDCEAOK9EK0tCS p4SRGKD6SpoqEZKVItacGfLLAjJeGt6kIDBdRJ0J/nASVgcvaT8= =DMVU -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9nQACgkQmmx57+YA GNkM8RAAqwYUKHl1pkAnTBU60aW9dWJpNdyIej22sdi+FcsGcF4tC/RQ+Zssl0VD eMvAM295eGZDb02B0f8EbPQHuDEp7Y9mpC+9QjoBCLCojho15ise3cKmyloG9/7T xo1J99lY/PW7ociVXqO4rZtWsplgy+FB3X+cCsk/UziwsF+HqjSSOi9VsEkHsBHI sJwDE90YetuC3S2+5/G9z2JbuqNchGebT66ZE13CGGBLb1cKBNMb2L1ZjwRlbhUK tYPBaTBnwJApLKoTQx4HlpAei5XROEB/3qxPH4e4RnW8MZyG7+ZNXnkIuZytJxVc zt5Qols2bLakHms0QdZhpeinvqPV4c88xGCZryQRHqbU1VLfygFFuoqnDfn/l0vW KWceaSMeL5EpvE+1sZsP7EcQn5AhCKckWoaL3TRJzeR/0JJswgBMMSBYof/eSP4u jJX+NBid6Hjred7B12QBFYc7L3LCDcmFmQM9LYa7IciedRx3fqw9yNRXzBVgTUDC t/cuLn06uLYTbn5fNnxxRvvDkLnXtf8OyzER0fy+Dm+terjIMATK3iQ0bGvwj46Y sQ74A7mQ+tsosmS+SEz79VD3AuzCqm3nfFTeU8W0QUj3IK1zqWKEjmJpeeniuL8L QBP7ZR8wlytfwq4fm2gI3wss1gFw8GYcJlkPhBAuHjMisiFWl10= =blMU -----END PGP SIGNATURE----- Merge tag 'ixp4xx-cleanup-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/soc This cleans out the remaining board files from IXP4xx and makes it an exclusive device tree subarchitecture without any special weirdness in arch/arm/mach-ixp4xx. The biggest noticeable change is the removal of the old PCI driver and along with that the removal of the special DMA coherency code and defines and the DMA bouncing. I tried to convert the IXP4xx to multiplatform on top of this but it didn't work because IXP4xx wants to be big endian and multiplatform config creates a problem like this: ../arch/arm/kernel/head.S: Assembler messages: ../arch/arm/kernel/head.S:94: Error: selected processor does not support `setend be' in ARM mode I think this is because MULTI_V5 turns on CPUs that cannot do big endian, and IXP4xx turn on big endian. (It crashes if I try to boot in little endian mode, sorry. It really wants to run big endian.) But before fixing multiplatform we can fix all of this! The networking patches are dependencies so I am requesting ACKs from the network maintainers on these. * tag 'ixp4xx-cleanup-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: ixp4xx: Convert to SPARSE_IRQ and P2V ARM: ixp4xx: Drop all common code ARM: ixp4xx: Drop custom DMA coherency and bouncing ARM: ixp4xx: Remove feature bit accessors net: ixp4xx_hss: Check features using syscon net: ixp4xx_eth: Drop platform data support soc: ixp4xx-npe: Access syscon regs using regmap soc: ixp4xx: Add features from regmap helper ARM: ixp4xx: Drop UDC info setting function ARM: ixp4xx: Drop stale Kconfig entry ARM: ixp4xx: Delete old PCI driver ARM: ixp4xx: Delete the Goramo MLR boardfile ARM: ixp4xx: Delete Gateway 7001 boardfiles Link: https://lore.kernel.org/r/CACRpkdahK-jaHFqLCpSqiXwAtkSKbhWQZ9jaSo6rRzHfSiECkA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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c845b55859 |
AT91 & LAN966 DT #1 for 5.18:
- lan966x basic DT and associated evaluation board pcb8291 (2-ports) - documentation for an upcoming Kontron switch board featuring a LAN9668 - one fix for an old bug we have with PMECC on sama5d2 in some corner cases - sama7g5 and its EK: crypto, CAN and DVFS operating points -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYhi3WQAKCRAfOrpwrNPN DOTGAP9y9/HV8EXrGhm8ZvH0ScfIkf3cPFyoFKtcN4EFNKb12QD/aSjSW17XEwTt L+RYm2x2lha8eVUteyRpZXZqmK8buwg= =3qii -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8xQACgkQmmx57+YA GNmEyg//ej6i6g/4dVcG1TQ+Fm4zSm19HM338FduYw2esH0P6pgUKG+V6sOBaFWF m2HaHPTsbaY90mshpym6rmC22UwEsdw64x5Z4en20NRrdLBjraVzLltz8UhLAEH2 +/pjw0CU/CxRE1z+OItfdElg3+HyJuPyF7rjXXCsM3DIMZzOR8CEXO9tt+K2EJKQ LgO5cz4a0lS6a0FUdXivq1jzRmQW2sUzvA+7XQ/KKczxLiNzgVWD92ysua9pzoBp a1eOrpr9BD2PpYawLlBQB995NjRCvgCf4P8QJDbjrOpfmbM13AqFi4Yk7LbKIY+d kvqp7Ru9Zbbvg7WW276jQOMbD53/AkmJEaomKsEJeazpvOOiDnMKsY5y0PZ8Ma/f +HSjAoXUSGw1x3+o/Ai8LlnOU6SXYo95OgmEz/KOpw08lBOkyWT2jSWEF+7bLHDg zw0vUQESSNsGMlfH1xWit9MLqlyr/WanAhQW3CKvsFfd8IEEo7dcA/djjWsTVgiS R5F9qJwq5/MLpxSESRJrUiVg5zBALEToHAdL+TsRD6aU0yBhsawaPQG2vWtCOdTw GIzY4GdYMo3izMDNaxcf+/ku/AjuCzTJGO73BKGrrY/e9Rk3vTBlNTp7FGBRxpb5 tu+X2uyXu8cMqzHcO/UYX7WN9OjVSIwFhS2Hf/3joK8ETxGpyy4= =+JfK -----END PGP SIGNATURE----- Merge tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 & LAN966 DT #1 for 5.18: - lan966x basic DT and associated evaluation board pcb8291 (2-ports) - documentation for an upcoming Kontron switch board featuring a LAN9668 - one fix for an old bug we have with PMECC on sama5d2 in some corner cases - sama7g5 and its EK: crypto, CAN and DVFS operating points * tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama7g5: add opps ARM: dts: at91: sama7g5ek: set regulator voltages for standby state ARM: dts: at91: fix low limit for CPU regulator ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek ARM: dts: at91: sama7g5: Add can controllers of sama7g5 ARM: dts: at91: sama7g5: Add crypto nodes ARM: dts: at91: Use the generic "crypto" node name for the crypto IPs ARM: dts: at91: remove status = "okay" from soc specific dtsi ARM: dts: at91: sama5d2: Fix PMERRLOC resource size dt-bindings: arm: at91: add Kontron's new KSwitches ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 Link: https://lore.kernel.org/r/20220225110735.18080-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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eda2a6830f |
Renesas ARM DT updates for v5.18 (take three)
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
-----BEGIN PGP SIGNATURE-----
iHQEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhjYwAAKCRCKwlD9ZEnx
cKSXAP0aBTnnmwZauIy0QIa2YGrGAqaiU1q++b0LV3iygbinSwD46Goz5adJeXrZ
+wta4wt82uakJRUdwouY+wBR4bPODw==
=kgbD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8vEACgkQmmx57+YA
GNn3OQ/+IhJ3AtsNRjl2YK5jBsXggax+Af4lVyB9ihBDN1HyWa1y2QjMRFcBmviY
Q/F+OdkyXNi6bUESDC7oCeZRqrW7qcw8gjy6ItPPgQC7UfUeluBxVedxbw+y7Mvm
8zwca6UPjOw4IdJgwCMVslSvqZnoiuUjJFacYQ6k/l8JBeKiuPDytgwx9tG0BXkV
Dps71xdxScpp55KyLYqU7MR3j9f6VtnP/46rdTs+xecRoASElrsXxojt0R6NLufg
7rtKoFzLNXHDR9L4xJNNgWVoq50OCK4nsZSFk6LZVQmMgpwTzA2V4zGEeWqLZsMw
Mey/RV7rG1T1YR3BY038BIaqJ+TnCbLXgp2TaEa6vgE4P8FyswobPRDZrzaVPSIc
gY2GrpmtonuIol7Ew8NSe9Mj8EbxPva95S3zK/XFdjHvb/9nG5hRaoN6dDEiF9ln
JTD0eWL5j9cPuzUtann49lbPhljnRjwRLWu42Sz1LQvpyHbNQPr+B6jehhJj7Flp
XVvSM3kczoEXEz4dzSqAo7SRMC2QC06luv5KO8J2uxwz3QYQo/1FEDxzM9Y11mZx
8nEeh4c/bWJ9b1Ob+PkD8P63uzizEYXeaMq7MrBXhNRoZGthga6QbiSlt0bv8B7m
iYCsEnzueJTz5X/70P5uYGltiQtQ5k2HHvFwA/jf1YrNEM4JIT8=
=61Bh
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take three)
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
* tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider: Complete SCIF3 description
arm64: dts: renesas: r8a779f0: Add pinctrl device node
Link: https://lore.kernel.org/r/cover.1645795643.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
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Arnd Bergmann
|
b10e270dc9 |
Renesas ARM DT updates for v5.18 (take two)
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhiomwAKCRCKwlD9ZEnx
cHPXAQDNxh5Fr/t8POQlZRhXr/qw9vSkP/bslbLBXIxQmtTuiAD/QOwd02UBun5Q
ei27RcXBOmzpxJBD281LL2fF560h9Ak=
=gcXB
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8lYACgkQmmx57+YA
GNnvkQ/+KA3wN4WIuWG1DfkRh3wOL06EtIlbMTomH7IGvPkPVI6s5lYgPN85pWOb
Sq50/TRTX+Lo3wU7bHWm6D4uik2i7haeFLXLnMm4p020OggqZlFlIStIg2AcZ4Mb
Xu4NFHKlBEelNW4r5lgWpVwpfX37NJb5dY/ZX/oW8fNzTGufGGN/QHLKXzyIpw09
gWTL6d9EIiY6up79mX48RHQ/lLjNLs/8Ae0nnmtHRp3268vGUaUhI1ybzKdAWfsg
0pgAk2bF5oPxpkMDe4/0cilB/BDHF2TRgt8/yXXJZ34EQTXciKu/Zi3n4CmViAHr
aPm9pF9SFFuiTS0PyeY9fyj3gjb3/vj0h6Slyr/U7b4YchdVJ+wLduued3hr0tJt
3LBKtAtxgc0EqOxf772UtWcd8ZPfDH0nJnAbEotZV7y03VRWK/eKgwIQ/j5kc9go
rSZ6Gc/2YeexK5nPSxir0XDelQjVDSRo/yDQmoSPvduUJrga1N4p1MVLSGvmWimB
o/oISmNVvl868/kMTmv9RwZlmULMAgjIqQ2yrwE1kCc2x0p04aWFRoYv7e++GG3M
tK/TvodD4BvjTDVPUMrG7Az5QPjMs8QbLIIGjulGcxwPlRW6tn09Eha+qTcA4X5o
tpyk5zPZDkw+MdixdjuBCkrD8Y6yFG7foRf6Rmnhqh9oClQmplk=
=WR66
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take two)
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout
ARM: dts: r9a06g032: Add the watchdog nodes
dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock
arm64: dts: renesas: spider-cpu: Enable watchdog timer
arm64: dts: renesas: r8a779f0: Add RWDT node
MAINTAINERS: Specify IRC channel for Renesas ARM64 port
MAINTAINERS: Specify IRC channel for Renesas ARM32 port
arm64: dts: renesas: ulcb-kf: fix wrong comment
Link: https://lore.kernel.org/r/cover.1645784466.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann
|
5a29ea50fc |
Remove an unneeded status property from the crypto-node
on rk3288. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIX+fYQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgXwbB/9VDhyjvWSdI/HNytYbMjCaxVv8S1PRZJNE I3dAxAYCfG50I8ztvuHBvv0V10x23jI0u2pnelk6kOTbYcCYI+dv7FnJ7oTa1G3I 4Sd8SAEVBeZ4lDlLgaQy4vyPYNIPxhfPwqNlAmGoRAG+RBcc37gbzf5Nmane4Uff B/H7zBIZ6gXRAuVMSJDMBKPHAQ+8FCbdfdfSzR/4haOnOAaiiMPELWwRgbLingvf u5G6EMbDw2dFVt/pHKiwGQtkwrNpMuSP1L072wAjPdoJfjpOyyJrHC5b3M9NymHp T76R2YnXBnO79vHS/+vu4vgJrQvP9p7TNyE/f+Ln6wUDvQmaLuyI =3tj2 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8i4ACgkQmmx57+YA GNmy/hAAh9HSHRuGnLTXo6706dAozI8ZTuMqutGW7y3Jpi02eK/Y0J7/k5p8HyAJ VhIBprYg2k4JGNhlSDzG6mqkXzgnBkKYlefc6hll7fZkxT2BAVGFTWcV4JCW1ziI 6mpN0PIbGej7XHAvax3l7ygdnbDPpCcfaAESpqffgILjK7rp5ZTL2t+MMmUqW8kW Qrgb6xD207idJ1eVCTUZjvXRCsYLw3ZuytWLriwudyWafl1m384NK52sRgWqVNUW ZIrsqKZwtH8EeHDzQMzj3ucGBqONSxYrDrl5L2vmnRM5IRWrfp4bogvyveBc4apf 4GPi9pIEHBGm6OOIV201x3BW5RikpvWKKbapcmap8EcZexfb8oDKBPBcZ6C7BhOL bzf+FExpGfgRD/itqGWi4Z68Qtk/IyeQBIg8FnR4WAbuEzNDYmD68KPeaQfG1fto aB6eBRurPU6RL5B8lsBSofD7whipPUqK3sTCPju9Szc6avdkDIWOSIg7aH1BdzAW tlzgigrVnpPjIg9H2WFkmqRIM/x7r6U3cJicuLdMSKoOBLDozXXFvOSMn0BiSXZI NDKjK4aJHoWJcb10VD5F7QvEhJYBpY8hZ79JdcXpkkzBg9EZn4vPGQn05gC1rqJI mPmLF9dZcDfpJ+i3rVn566dFnlsKmrPeESZpNqVvu4a0U9KnaJA= =SM/M -----END PGP SIGNATURE----- Merge tag 'v5.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Remove an unneeded status property from the crypto-node on rk3288. * tag 'v5.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: remove status from rk3288 crypto node Link: https://lore.kernel.org/r/19595245.eudUkVceaq@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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84d08b2e54 |
New boards: Pine64 PineNote ereader tablet and Bananapi-R2-Pro (both rk356x)
New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2) A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains, usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led, usb2, touchscreen). Fixes for the pwm-regulators, that used wrong names for their supplies as well adapting the cros-ec pwm nodes to a changed binding (going via the pwm tree). And as sort of misc-changes, defined the logic-regulator on rk3399-puma as well as enabled the mali-gpu on the rk3399-firefly. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIX+P8QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgfZLB/9DUe9pJWRo7zg3GENlp9d3slQBJkBWHF4h SiYheGDbQyfWmPeH4PcvwfwsVmTdNewRTgmhEbNKyl64XEIEbIVi7GXEmfCaNipQ zEfTN/m1hMl1kn9gey+0yJT9K3oAkA4UqBUbGmgP/UuYcztZvnhjnt9Np60gwBhf l7de3OBFcxQUatq2Tfn+HbqiGA5aur/IfJzcrzK9kFXLi6Ox2nMZGN1U2CTmJEcT ZLFQH1tKQ0doacaAUtRSSx3IbTVSoOjr2imSzsfPKCM691OwwGC4XeJLVTn3QmVF 4WhDQsH+ufluG/dFHPA7Nqa1IVp9IX/QhOW1ZAgmODNVR37EkXGp =cIwM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8fUACgkQmmx57+YA GNnjPw/+LYwi3YXP4izmG0u6y/Jfmy1J6T37FCZJEo8C9I92USUU+S6z9pEG5yrn LhmXogJj3zB6dGUcq7nFUXIUA5YMVGxofnFRbyxbGPUmRnQSfpOB2/g4aSEYf2U8 0OwD/4ajxVOP2mSimQ7gXnwpzfeUvNrml81VJ76OHZnVtEqt81l/vIyWpd3Dro00 EQN+THTAV4G2M6XhshILt5QTLdsWHwPoCaZAg0PwmIJDU/3NeBH92rXIQiWkE33R zmPJyOZ2ih3D2ceyVVdNp9uIvLcXeIpsXqIQv2dN0D5iXjviyBqfX787S4PFLlLO ibsYyB+JUkciwzHyRrKHRYlOXuZmhYDYcL1M+6STSMtmZfS3Kno6V9kOdPYWpTZ8 SluJYqdkED0NMggegunGj67qbe902hX9vuL3vISaZUll3Au48YGSEoEcpghf8kuE E2Uo4pnEkhN/1sSeZFyINUstKtqpa/XMAS2sK/CJQ09HjQfqvFnifjUxhjqYoAM6 ylhjDymjH11h3jWDmiJUpYfPxa4u/j598UI4ajvKgwPhd0ZxLug43d9IQBpFxux6 qXCWQrgUe39L5o8hfgQSXb58g72uGBXMRd8m7F3G52teGkFz+xentxHbJEZlX8oZ UQJXCDHhkFpGkD3TNOc4YbQW/ydDZo+OCzWopP3iU6oG2X3FPQY= =yqpJ -----END PGP SIGNATURE----- Merge tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt New boards: Pine64 PineNote ereader tablet and Bananapi-R2-Pro (both rk356x) New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2) A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains, usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led, usb2, touchscreen). Fixes for the pwm-regulators, that used wrong names for their supplies as well adapting the cros-ec pwm nodes to a changed binding (going via the pwm tree). And as sort of misc-changes, defined the logic-regulator on rk3399-puma as well as enabled the mali-gpu on the rk3399-firefly. * tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (28 commits) arm64: dts: rockchip: align Google CROS EC PWM node name with dtschema arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10 arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always on arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10 arm64: dts: rockchip: enable work led on rk3568-evb1-v10 arm64: dts: rockchip: fix supplies for pwm regulators arm64: dts: rockchip: define vdd_log on rk3399-puma arm64: dts: rockchip: Add Pine64 PineNote board arm64: dts: rockchip: Add pdm node to rk356x dt-bindings: arm: rockchip: Add Pine64 PineNote board arm64: dts: rockchip: enable the tsadc on rk3568-evb1-v10 arm64: dts: rockchip: enable the gpu on rk3568-evb1-v10 arm64: dts: rockchip: enable the gpu on quartz64-a arm64: dts: rockchip: add cooling map and trip points for gpu to rk356x arm64: dts: rockchip: add gpu node to rk356x arm64: dts: rockchip: add usb2 support to rk3568-evb1-v10 arm64: dts: rockchip: rename and sort the rk356x usb2 phy handles arm64: dts: rockchip: add the i2s3_2ch node to rk356x arm64: dts: rockchip: Add Bananapi R2 Pro dt-bindings: rockchip: Add BananaPi R2 Pro Board ... Link: https://lore.kernel.org/r/6456947.djgVdjDsCv@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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ceaf23fe3f |
Usual round of DT patches for the 5.18 merge window, with:
- DT fixes - ethernet0 alias for Nanopi NEO - r_uart node for H3/H5 - eMMC and bluetooth nodes for Nanopi NEO air - updated maintainers for Allwinner SoCs - new board: A20-Marsboard -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCYhf4hQAKCRB0Ba7+DO8k k/78AQCri8W0S4biFkv9CkzDGF3zioN6f/nlkWg4IWWdCFFY7AD8Dhv6UQm2j4HZ sp1ipPUlHVcIknYhPX2jDbmOV/dt8gI= =Vuzk -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8aQACgkQmmx57+YA GNn8/g//bZBlICtTJPQTwv0gGFqF1whlItzggEsHNQvCluOlEob2DWj2MmtbDjDm F2J2fN6F0TXUIlCHTrxpU2r5HJvQnyZV/xKhwWXa4bi/fTbhZyD45duoltqy5U2e ss8g7KleA1UZ9X1FIStHYapN2FXkaujCJouVQNksVLXjmxQnmcvVTYT2fRKpAWO1 9523MR2z5w1/nneaBbw/K1hCkW1YASlfgdpiZ+oDMFWAwZRelk4nFY1Uotd+wYw5 1DTl2R0m70k3apwnbU/zerSvZ6Lu+WRJE6Su7DDFv5j8mM7KtaQV0yULXY0oASkT 1xqYUi2EJHYtQQXXat5XEKyvwPsmQVwLfyQEHgsup3mPWq8aZtdRQ1HH+hdVvuZO 19HLmPvKR6tuey4ujaHpWJmP8kCvHMp35b4wiv56NatYym5tG6vcOTiBGZdthILW +xAMcW7Hx96xFdVVBU/OnlyFxL9tquA02XkDPVhY9pHu4KGmhPAxqsv66Exf/mKX 0mOXXA6GC1gnzn3Fuy75WpUTA5K30M3gRQ28xbltqI4f1sMgxGScgxVAOhSuuBJ7 Dr8n4r8h4oegQ4eApF30XyxcYffgY8KTDOlWskYGCzdSboiG62a2yI26rhp/I0Gx a5Oq7Fm58bh6CnvzSkWBMJj1Ql9hpvmVCVeNUzQcRiS/X+8f8IA= =36rC -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Usual round of DT patches for the 5.18 merge window, with: - DT fixes - ethernet0 alias for Nanopi NEO - r_uart node for H3/H5 - eMMC and bluetooth nodes for Nanopi NEO air - updated maintainers for Allwinner SoCs - new board: A20-Marsboard * tag 'sunxi-dt-for-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: MAINTAINERS: Update Allwinner SoCs maintainers ARM: dts: sun8i-h3: Drop args in 'thermal-sensors' ARM: dts: sun8i: v3s: Move the csi1 block to follow address order ARM: dts: sun8i: Add ethernet0 alias in Nanopi NEO's device tree dt-bindings: arm: sunxi: add haoyu,a20-marsboard ARM: dts: sun7i: Add A20-Marsboard ARM: dts: sunxi: h3/h5: add r_uart node ARM: dts: nanopi-neo-air: Add eMMC and bluetooth Link: https://lore.kernel.org/r/YhgMJ0AqaHopzaW3@kista.localdomain Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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e03e97d5b4 |
Devicetree changes for omaps for v5.18
Devicetree changes for omaps for v5.18: - The devicetree node naming for pdu001 RTC name gets corrected - For logicpd-torpedo baseboard, isp1763 USB controller gets added - New board variant for SanCloud BBE Extended WiFi gets added -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmIV8/8RHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXP9EQ//RP3aHRVqpLihhsJuXzpYOA3mjzqoTMX2 +BZOwFuU9+8FNKkiLO2CmIgQIlKMYsw8020aAskfSYnPjToVI5eM75ZhIbpVzJRZ OnJevrf+fzTkYyYhiS+3enyha9QoCf4/bGrKYXTxOUQmsclnnsBlrAir5zkVKM90 CCTnbj99bV1ycMMZdk9kgiNTR6skoTaHLGrVL1/pzLAWMijiecE+d4FHNHETBKzn 4naywy2G/1KshCepOmx6QM5oExTOFKV531Xw4U/zZpku+SMWDTbwBGjNt5FXuT9K Fa7dzoXZm7Hky4h6iioySWvsISrc325ft2RmxfHNYhc+9WraFxAZUvuzaThBrRdZ tSjOnFTq/Mm33TKZH4dFVQxnIC+4m6mC58+dI5aAIUXNs3rL6xbEyR2BYmj/e0BB mv8HuWI2JxGWII9QJvTbUASyH4lpYI7jAtYtwvsE5xYCvYMRnqZoEgvGxHrxlAw8 n3m5qjO8urBFOKw1Lz5+aHeB9aUBw+U4OavculEaZTswo6pCaNoofjMVLe37cMxc 08x9rV+X4wnG8VYHtP4YKx3QTDgmSw68ASd6B6Z0mJWhjEbyqtFpgRsXxsaSoLgd FoagqnJJDBKtAWhiM01cfIDRX9leyNWVoRuc8+uG4wqTRmaqKWlrF/1bEx7eqfUb lAemYu2E11g= =5YEO -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8X0ACgkQmmx57+YA GNlGbA/+KmVWLJCd/W8S1LsDYcRH/jED722NNdjw0IV/GyPKLWzo/P06nCtSwYGQ NsJYWbvufThNHoagkzohdmm/mithgaEcQygtO1H6KvhLY/uEo9uE2wQxIIJFN3ZI djmPTD8pLSXl6by8XegVNkqrqMdaa7k9P2dHL3hPimWR5k2wH2YQBfIc9kwtoxzS BKLXyUORaEdsHfum5SuHtHmUtEvy0SA3B0y94viKhELjvbGiKmLixuo0jzcLckTd UXKfZp3WW3eCwkOQuqeVem/pN/lJtvn77mizenoJ7D1B6DOJ7ZiRCmSpWS5egVS4 XCGxHdInEHi/oqiMY6wpe0UxqmsdtLSMJ7r96WsH5Lc8/lW9fX42ugxA8WzrvPH+ mwyI6KRyVrVjDeFp7d9MAryXtuk0/2GAL+6SLgqDYolgewTm79Is2tm9LYtuhvRg bklaWOQiCc6jTN65KUOqYSlIzMNKf8a6sfOMKJTQB+KYYSZ2hg5ZCTWXUUYFMkSr FSDYstzOj6KyIddcHLQEs+sYdaec0XKDt0kWjl0Y/fxhjjU4ELRdce0F9kxuhIgm LPRMt+H5i4WrxZnYPPm+uTIa5RlhW2fHWZcXi+1RH8s3/unoG3SWWwRXY+VVIIKn ixEEv4CeXmNWgCj/M/FZIRSsLK2+b2145i8F4Cpga4czggBkPcI= =HX09 -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.18/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omaps for v5.18 Devicetree changes for omaps for v5.18: - The devicetree node naming for pdu001 RTC name gets corrected - For logicpd-torpedo baseboard, isp1763 USB controller gets added - New board variant for SanCloud BBE Extended WiFi gets added * tag 'omap-for-v5.18/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-sancloud-bbe-extended-wifi: New devicetree ARM: dts: logicpd-torpedo: Add isp1763 support to baseboard ARM: dts: am334x: pdu001: Use correct node name for RTC Link: https://lore.kernel.org/r/pull-1645606669-127734@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Li RongQing
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9ee83635d8 |
KVM: x86: Yield to IPI target vCPU only if it is busy
When sending a call-function IPI-many to vCPUs, yield to the IPI target vCPU which is marked as preempted. but when emulating HLT, an idling vCPU will be voluntarily scheduled out and mark as preempted from the guest kernel perspective. yielding to idle vCPU is pointless and increase unnecessary vmexit, maybe miss the true preempted vCPU so yield to IPI target vCPU only if vCPU is busy and preempted Signed-off-by: Li RongQing <lirongqing@baidu.com> Message-Id: <1644380201-29423-1-git-send-email-lirongqing@baidu.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Dexuan Cui
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92e68cc558 |
x86/kvmclock: Fix Hyper-V Isolated VM's boot issue when vCPUs > 64
When Linux runs as an Isolated VM on Hyper-V, it supports AMD SEV-SNP but it's partially enlightened, i.e. cc_platform_has( CC_ATTR_GUEST_MEM_ENCRYPT) is true but sev_active() is false. Commit |
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Wanpeng Li
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3c51d0a6c7 |
x86/kvm: Don't waste memory if kvmclock is disabled
Even if "no-kvmclock" is passed in cmdline parameter, the guest kernel still allocates hvclock_mem which is scaled by the number of vCPUs, let's check kvmclock enable in advance to avoid this memory waste. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1645520523-30814-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Wanpeng Li
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40cd58dbf1 |
x86/kvm: Don't use PV TLB/yield when mwait is advertised
MWAIT is advertised in host is not overcommitted scenario, however, PV TLB/sched yield should be enabled in host overcommitted scenario. Let's add the MWAIT checking when enabling PV TLB/sched yield. Signed-off-by: Wanpeng Li <wanpengli@tencent.com> Message-Id: <1645777780-2581-1-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Arnd Bergmann
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1b29d1c1fa |
Arm Juno update for v5.18
Just a single update adding long waited support for SCMI firmware variant as separate devicetrees. I wanted to deal with this differences in the firmware interface within the bootloader for long time. But with variety of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI support for sake of discovery with discrepancies in shared memory layout, it turned out difficult. So, finally we are adding it as separate files so that we don't break support for older SCPI firmware interface. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmIVQ7YACgkQAEG6vDF+ 4piUsg/7B/d8NBgfXQ4WSVCDw7D5ekkTVSA8I1jOu084UCUCoQjJ6h9I0sMc8ALo ikYRgF34evJP78xl+AGsU7iQfeja4i4j+5frUt9pseiQ3XW7i+kFmp/bjX9XlYFQ HsGJ+F7oUp70W5YxfF+Ay1I9avbA6hDWqSE6gsFNVPRnVpphBzF7MvBBsTdl9CE8 ip/gTg2WEnjzdvCHyCQ9wGV8HozTtcR2Fz1WB3LaIpqToIui7gQ2KEazqTH5cJcS xovUdM5eMdvMHsblnLDn/ET6gvFlV1AeRxUQXQTDm8tqk/3cpRzZj0EcWJy2A6OE 0BQ63bw8bwqR+JW/vbhW01PdaA6uuKhKNINuP/RtCv++/UimDyI4QgRs8MzLFUYH 2JKptVQpaeracUElKNBkOGZGhzS9p8I9smzhFyZVHucBQA0vDzOX7e2BJpLyhTJV tnRMc+mUH6KHr97eEJxFiEVC6aI3UiaVgTjaMnEB7ED8yWa6x0bLbgX9RRhXj9W9 hNOuCMBuDhQZD86wVwUXAi2yB0UHlCNbmhEoegxaL0h7o1G0GyNB5crLMZwck4sy CCaLUZbUaJrsFaVpv5C6/M2xhwUtf/yKDlW65EduBc6KFKiZa4c1mrE+Ft2ZqD79 bVVLlzW/lz+2YdITrbyCCbzgNyQhwp4aNqHLwlwuDsSzhSD5uZ0= =g/zs -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8SUACgkQmmx57+YA GNmySg//WaF+/WTHSYleBvknbsmMQjvYz9LqpQmAXlJkxqnrbORgiBVByQ9SNgKg Pkz6j6Ex4se8KfzZUwMmdGhuN+pOWQKi3hd2YZtt4W5koTuVw9pDberafiskC7fV IGqdYvJtDBWZdlFfE9RZAYEvFt2cAHQJEBQQiNX3cgRl+RgqZpHC8Umm/1mLAo2a MgLRVVRkONxQN6DPtb6KOrLqWGmVo9+wDhDXHLqBQIMyHHj/fMuNOc/c98ePPUPI Z/0Rk/z8+Bt+6lc0FtLSjljSuSphkm//5IVle8v1KKAH3Iq0cmnjFAaXRH168naa oR4vyRFG7i+2syFHrSt5wRmsqQab99lyqwGUgNsD7+Fl+uxt53T0z2ijIDzP3aZE SyaQxwLUMyinPhppGNG7KoK7VEMqBpYJnhrtbDO8knrQK8SjFQY0t378lUvOFGPE orAGkNX5P8FH22zq/qsJT/ls8qQ6nC/fe/5g8tNcLqbO88hSmLd2yacRp9U1UOST ekVZZjQeDoWukPN11fSwSvKzrzx76xohtrN4NPzH+civuwr+J36PNz6R0nI7FDp4 ngs06jZztgNs4fItCmUhVgz2cgk96VDr8AZ2Fzt9+A4sPUcZWqy1yr5aip4/vVTE LwTvzPIiL4zWBosx0J2XaYMIPwUGtY35bYmHxavYeNPLMEgSS00= =D501 -----END PGP SIGNATURE----- Merge tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt Arm Juno update for v5.18 Just a single update adding long waited support for SCMI firmware variant as separate devicetrees. I wanted to deal with this differences in the firmware interface within the bootloader for long time. But with variety of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI support for sake of discovery with discrepancies in shared memory layout, it turned out difficult. So, finally we are adding it as separate files so that we don't break support for older SCPI firmware interface. * tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Add separate SCMI variants arm64: dts: juno: Remove GICv2m dma-range Link: https://lore.kernel.org/r/20220222201812.3338619-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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52e71a47e8 |
i.MX arm64 device tree change for 5.18:
- New support for a number of i.MX8M Mini based boards: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903. - A series from Adam Ford to enable GPC, USB and display support for i.MX8M Nano. - Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ. - Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk, imx8mq-evk and imx8mm-venice board. - A series from Hugo Villeneuve to add PCA6416 interrupt controller configuration, GPIO line names and i2C5 support for imx8mp-evk board. - Correct I2C3 pad-ctrl and add internal display support for mnt-reform2 board. - Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding and using overlay target for build. - Add overlay support for serial modes and imx219 rpi v2 camera on Gateworks imx8mm-venice devices. - A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM device tree, including drive strength updates of different interfaces and PMIC configuration changes. - Device additions on various boards and some small random changes. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUi64UHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM7s3Qf/TtDGP7UBFb0nnqNgNzkiQfnxsRog iGcwwalE/Qn4Tq5ED/Sf34FOJut70fJ8chvbhqvCGkEOQPdgYOrFC8PmZw1VbKeX 5xNDihh3DAIEcGmJ89dDD5bkCepKOkyahm5c25RLzkUCOcKndoeWkzvU5bbMTs2w 8AJCrDmJ1+k5zyUXcKZlq3ySNhS4KQFD25dYGMvLy70oYhxCRtY/HLECLEStXVXs UJ5tdwPeb4jSLi5EM9oupy4V3IGfgBSSdFCLdpXtlOTmGg5Y5rHeO1E8mFRXvigO tCYo70SdzjLZPPxl9SUX6Ql7ShMYNZLtzmIVRn7Be2jRQ4xld9bXE4jFJw== =iEe4 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8JAACgkQmmx57+YA GNkUDRAAlwe2qrtugN8jUbnUIN41La5QiXOCAJYOQCosyCgAVb70ZGTIBJvOucyj bpwU3n4hN/nppMF47jct+RRE5UcPWNF4oB7LxgEe2SdqrkUmF9/moK5XjfipCTgr gvGln28un3mR7KS9cah3YFM/tTf749CeL5GiGx0veew39LxlYZMGA7wXIl1hJ1Tt Vl9jzfxsrVh+lzexQBJfAbWQAE4wM5WPwDl3H/o6xZGRZPCJkuNzdmZBvnZaC5WM ZT/R7CoeimHOV2936993MXjWkZqqZMaUBvrMGcoLYReq+0Qnht2hcETW/rHUa1+M 5nsPWSBfN8uN7jGP+qpz71eJbc8BQ/XKyximoJph9m3M1VbTNKjY1Lhq6dX2Fmyt cutVy70TGvOEjXJOctnWf973ABBhr+NnF5m0NAJ9XGsKEGI3j3tjgYO8rpcCVnm4 AdAqSv6/HF6PQkLuT/oJu8SfHzykvZDwkh+lAP2Hfnd+Y8DEkez+c96VkvW0lqzf TxrZIWQqrYGFPahB8rWjGzRPoLjJW6pfBEg/1iRmStMb2O+VQKzndf0DcYarrPjY 1ecrpGssvI701PP3ofwFoiOS4tGU/G955Lq8uKoT2DUVAXMOaaiGKUdxJyaMcfEr F4BK4eLvyn/t6XDzM+7Tfj1e054bbi9GO9JZFNbGwFLCOkzHurA= =atxP -----END PGP SIGNATURE----- Merge tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree change for 5.18: - New support for a number of i.MX8M Mini based boards: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903. - A series from Adam Ford to enable GPC, USB and display support for i.MX8M Nano. - Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ. - Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk, imx8mq-evk and imx8mm-venice board. - A series from Hugo Villeneuve to add PCA6416 interrupt controller configuration, GPIO line names and i2C5 support for imx8mp-evk board. - Correct I2C3 pad-ctrl and add internal display support for mnt-reform2 board. - Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding and using overlay target for build. - Add overlay support for serial modes and imx219 rpi v2 camera on Gateworks imx8mm-venice devices. - A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM device tree, including drive strength updates of different interfaces and PMIC configuration changes. - Device additions on various boards and some small random changes. * tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits) arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4 arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage arm64: dts: imx8mp-phycore-som: Update WDOG muxing arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support arm64: dts: ls1028a: add efuse node arm64: dts: imx8mp-evk: add support for I2C5 arm64: dts: imx8mp-evk: add PCA6416 gpio line names arm64: dts: imx8qm: added more serial alias to dts arm64: dts: imx8qm: add compatible string for usdhc3 arm64: dts: imx8mq-evk: Add second PCIe port support arm64: dts: imx8mm-beacon: Enable PCIe arm64: dts: freescale: add initial support for verdin imx8m mini ... Link: https://lore.kernel.org/r/20220222075226.160187-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |